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MFR4300
Data Sheet
FlexRay Communication Controllers
MFR4300 Rev. 3 04/2007
freescale.com
MFR4300 Data Sheet
MFR4300 Rev. 3 04/2007
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify that you have the latest information available, refer to http://www.freescale.com/flexray. The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date 3/2006 4/2006 Revision Level 0 1 Initial release - Preliminary. Official release Chapter 3 revised extensively. Minor changes to other chapters. Table 1-1: Added definitions for ID and PHY Table 2-3: Changed INT_CC# RESET value from 1 to 0 Table 6-3: Corrected ECS bit description (actions defined by 0 and 1 were reversed). Figure 6-6: Removed glitch from RESET# waveform. Table A-9: Changed maximum value of VPORD from 2.05 to 2.07. Table A-11: Changed "POR release level" to "POR deassert level". Table A-11: Changed "VPORR" to "VPORD". Table A-11, A.3.1.1, A.3.1.2, A.3.1.2, Table A-12: Updated to remove information relating to clock quality check block. Updated Mechanical Outline drawing in Figure B-1, Figure B-2, and Figure B-3 from Rev. D to Rev. E (to correct coplanarity specification). Applied latest version of back page. Fixed inconsistencies in naming conventions for ranges and active-low signal names. Added "Write Any Time" field to register diagrams in PIM and CRG chapters. Rotated text where appropriate in register diagrams to prevent line-breaks in bit names. Corrected any unresolved cross-references. Inserted "AC over or undershoots for +/-2V beyond the supply if limited to 20ns length are allowed." as a footnote for Table A-1. Corrected hyphens, em dashes, and en dashes for appendix. Description Page Number(s) N/A N/A
11/2006
2
26 37 223 227 246 248 248 248, 249 255, 256, and 257 Various Various Various Various 239 Various
04/2007
3
MFR4300 Data Sheet, Rev. 3 4 Freescale Semiconductor
Introduction Device Overview FlexRay Module (FLEXRAYV2) Port Integration Module (PIM) Dual Output Voltage Regulator (VREG3V3V2) Clocks and Reset Generator (CRG) Oscillator (OSCV2) Electrical Characteristics Package Information Printed Circuit Board Layout Recommendations Index of Registers
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 5
MFR4300 Data Sheet, Rev. 3 6 Freescale Semiconductor
Contents
Section Number Title Chapter 1 Introduction
1.1 1.2 1.3 1.4 Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page
Chapter 2 Device Overview
2.1 2.2 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 MFR4300 Implementation Parameters and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.2 Part ID and Module Version Number Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.2 Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Clock and Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.1 External 4/10/40 MHz Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.2 External Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.3 Recommended Pullup/pulldown Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 External Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.1 Asynchronous Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.2 HCS12 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.4
2.5 2.6
2.7
2.8
Chapter 3 FlexRay Module (FLEXRAYV2)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.1 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.3 Color Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 7
Section Number
Title
Page
3.2 3.3
3.4
3.5
3.6
3.1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Memory Map and Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.4.1 Message Buffer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.4.2 Physical Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.4.3 Message Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 3.4.4 FlexRay Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.4.5 Physical Message Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 3.4.6 Individual Message Buffer Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.4.7 Individual Message Buffer Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 3.4.8 Individual Message Buffer Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 3.4.9 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.4.10 Channel Device Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 3.4.11 External Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.4.12 Sync Frame ID and Sync Frame Deviation Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.4.13 MTS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.4.14 Sync Frame and Startup Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.4.15 Sync Frame Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.4.16 Strobe Signal Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 3.4.17 Timer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.4.18 Slot Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 3.4.19 Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.4.20 Clock Domain Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.5.1 FlexRay Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.5.2 Number of Usable Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.1 Shut Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.2 Protocol Control Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.3 Protocol Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Chapter 4 Port Integration Module (PIM)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
MFR4300 Data Sheet, Rev. 3 8 Freescale Semiconductor
Section Number
4.2
Title
Page
4.3 4.4
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.2.1 Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 4.2.2 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 PIM Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.3.1 Port Integration Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.4.1 Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.4.2 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Chapter 5 Dual Output Voltage Regulator (VREG3V3V2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.1 VDDR, VSSR -- Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.2 VDDA, VSSA -- Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.3 VDD, VSS -- Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.2.4 VDDOSC, VSSOSC -- Regulator Output2 (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.1 REG -- Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.2 Full-performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.3 POR -- Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.4 LVR -- Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.3.5 CTRL -- Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4.2 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.2
5.3
5.4
Chapter 6 Clocks and Reset Generator (CRG)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 MFR4300 Relevant Pins for the CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 CRG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.1 Detection Enable Register (DER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.2 Clock and Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4.1 Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 9
6.2 6.3
6.4
Section Number
Title
Page
6.4.2 Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 6.4.3 CLKOUT Mode Selection and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Chapter 7 Oscillator (OSCV2)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.2.1 VDDOSC and VSSOSC -- OSC Operating Voltage, OSC Ground . . . . . . . . . . . . . . . . . . 233 7.2.2 EXTAL and XTAL -- Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.4.1 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.2
7.3 7.4 7.5
Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 A.2 Voltage Regulator (VREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 A.2.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 A.2.2 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 A.2.3 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 A.3 Reset and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 A.3.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 A.3.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 A.4 Asynchronous Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 A.5 HCS12 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
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Title Appendix B Package Information
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B.1 64-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Appendix C Printed Circuit Board Layout Recommendations Appendix D Index of Registers
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MFR4300 Data Sheet, Rev. 3 12 Freescale Semiconductor
List of Figures
Figure Number
Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21.
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Order Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MFR4300 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MFR4300 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Square Wave Clock Generator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AMI Interface with MPC5xx and MPC55xx Families . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AMI Interface with S12X Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AMI Interface with DSP 56F83 (Hawk) Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HCS12 Interface Address Decoding and Internal Chip Select Generation . . . . . . . . . . . 53 HCS12 interface with HCS12 Page Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HCS12 interface with HCS12 Unpaged Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FlexRay Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Module Version Register (MVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Module Configuration Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Strobe Signal Control Register (STBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Strobe Port Control Register (STBPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Message Buffer Data Size Register (MBDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Message Buffer Segment Size and Utilization Register (MBSSUTR). . . . . . . . . . . . . . . 74 Protocol Operation Control Register (POCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Global Interrupt Flag and Enable Register (GIFER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Protocol Interrupt Flag Register 0 (PIFR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Protocol Interrupt Flag Register 1 (PIFR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Protocol Interrupt Enable Register 0 (PIER0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Protocol Interrupt Enable Register 1 (PIER1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CHI Error Flag Register (CHIERFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Message Buffer Interrupt Vector Register (MBIVEC). . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Channel A Status Error Counter Register (CASERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Channel B Status Error Counter Register (CBSERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Protocol Status Register 0 (PSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Protocol Status Register 1 (PSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Protocol Status Register 2 (PSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Protocol Status Register 3 (PSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Figure 3-22. Figure 3-23. Figure 3-24. Figure 3-25. Figure 3-26. Figure 3-27. Figure 3-28. Figure 3-29. Figure 3-30. Figure 3-31. Figure 3-32. Figure 3-33. Figure 3-34. Figure 3-35. Figure 3-36. Figure 3-37. Figure 3-38. Figure 3-39. Figure 3-40. Figure 3-41. Figure 3-42. Figure 3-43. Figure 3-44. Figure 3-45. Figure 3-46. Figure 3-47. Figure 3-48. Figure 3-49. Figure 3-50. Figure 3-51. Figure 3-52. Figure 3-53. Figure 3-54. Figure 3-55. Figure 3-56.
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Macrotick Counter Register (MTCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Cycle Counter Register (CYCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Slot Counter Channel A Register (SLTCTAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Slot Counter Channel B Register (SLTCTBR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Rate Correction Value Register (RTCORVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Offset Correction Value Register (OFCORVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Combined Interrupt Flag Register (CIFRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Sync Frame Counter Register (SFCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Sync Frame Table Offset Register (SFTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Sync Frame Table Configuration, Control, Status Register (SFTCCSR). . . . . . . . . . . . . 99 Sync Frame ID Rejection Filter Register (SFIDRFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR). . . . . . . . . . . . . . . . . . 101 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR). . . . . . . . . . . . . . . . . . 101 Network Management Vector Registers (NMVR0-NMVR5) . . . . . . . . . . . . . . . . . . . . 101 Network Management Vector Length Register (NMVLR) . . . . . . . . . . . . . . . . . . . . . . 102 Timer Configuration and Control Register (TICCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Timer 1 Cycle Set Register (TI1CYSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Timer 1 Macrotick Offset Register (TI1MTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Timer 2 Configuration Register 0 (TI2CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Timer 2 Configuration Register 1 (TI2CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Slot Status Selection Register (SSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Slot Status Counter Condition Register (SSCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Slot Status Registers (SSR0-SSR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Slow Status Counter Registers (SSCR0-SSCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 MTS A Configuration Register (MTSACFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 MTS B Configuration Register (MTSBCFR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Receive Shadow Buffer Index Register (RSBIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Receive FIFO Selection Register (RFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Receive FIFO Start Index Register (RFSIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Receive FIFO Depth and Size Register (RFDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Receive FIFO A Read Index Register (RFARIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Receive FIFO B Read Index Register (RFBRIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR). . . . . . . 115 Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) . . . . . . . . 116 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) . . . . . . . . . . . 116
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Figure Number
Figure 3-57. Figure 3-58. Figure 3-59. Figure 3-60. Figure 3-61. Figure 3-62. Figure 3-63. Figure 3-64. Figure 3-65. Figure 3-66. Figure 3-67. Figure 3-68. Figure 3-69. Figure 3-70. Figure 3-71. Figure 3-72. Figure 3-73. Figure 3-74. Figure 3-75. Figure 3-76. Figure 3-77. Figure 3-78. Figure 3-79. Figure 3-80. Figure 3-81. Figure 3-82. Figure 3-83. Figure 3-84. Figure 3-85. Figure 3-86. Figure 3-87. Figure 3-88. Figure 3-89. Figure 3-90. Figure 3-91.
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Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) . . . . . . . . . . . 117 Receive FIFO Range Filter Configuration Register (RFRFCFR) . . . . . . . . . . . . . . . . . 117 Receive FIFO Range Filter Control Register (RFRFCTR) . . . . . . . . . . . . . . . . . . . . . . 118 Last Dynamic Slot Channel A Register (LDTXSLAR) . . . . . . . . . . . . . . . . . . . . . . . . . 118 Last Dynamic Slot Channel B Register (LDTXSLBR) . . . . . . . . . . . . . . . . . . . . . . . . . 119 Protocol Configuration Register 0 (PCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Protocol Configuration Register 1 (PCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Protocol Configuration Register 2 (PCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Protocol Configuration Register 3 (PCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Protocol Configuration Register 4 (PCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Protocol Configuration Register 5 (PCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Protocol Configuration Register 6 (PCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Protocol Configuration Register 7 (PCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Protocol Configuration Register 8 (PCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Protocol Configuration Register 9 (PCR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Protocol Configuration Register 10 (PCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Protocol Configuration Register 11 (PCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Protocol Configuration Register 12 (PCR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Protocol Configuration Register 13 (PCR13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Protocol Configuration Register 14 (PCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Protocol Configuration Register 15 (PCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Protocol Configuration Register 16 (PCR16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Protocol Configuration Register 17 (PCR17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Protocol Configuration Register 18 (PCR18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Protocol Configuration Register 19 (PCR19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Protocol Configuration Register 20 (PCR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Protocol Configuration Register 21 (PCR21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Protocol Configuration Register 22 (PCR22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Protocol Configuration Register 23 (PCR23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Protocol Configuration Register 24 (PCR24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Protocol Configuration Register 25 (PCR25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Protocol Configuration Register 26 (PCR26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Protocol Configuration Register 27 (PCR27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Protocol Configuration Register 28 (PCR28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Protocol Configuration Register 29 (PCR29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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Figure Number
Figure 3-92. Figure 3-93. Figure 3-94. Figure 3-95. Figure 3-96. Figure 3-97. Figure 3-98. Figure 3-99. Figure 3-100. Figure 3-101. Figure 3-102. Figure 3-103. Figure 3-104. Figure 3-105. Figure 3-106. Figure 3-107. Figure 3-108. Figure 3-109. Figure 3-110. Figure 3-111. Figure 3-112. Figure 3-113. Figure 3-114. Figure 3-115. Figure 3-116. Figure 3-117. Figure 3-118. Figure 3-119. Figure 3-120. Figure 3-121. Figure 3-122. Figure 3-123. Figure 3-124. Figure 3-125. Figure 3-126.
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Protocol Configuration Register 30 (PCR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Message Buffer Configuration, Control, Status Registers (MBCCSRn) . . . . . . . . . . . . 128 Message Buffer Cycle Counter Filter Registers (MBCCFRn) . . . . . . . . . . . . . . . . . . . . 130 Message Buffer Frame ID Registers (MBFIDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Message Buffer Index Registers (MBIDXRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Physical Message Buffer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Individual Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Receive Shadow Buffer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Receive FIFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Example of FRM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Frame Header Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Receive Message Buffer Slot Status Structure (ChAB) . . . . . . . . . . . . . . . . . . . . . . . . . 146 Receive Message Buffer Slot Status Structure (ChA) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Receive Message Buffer Slot Status Structure (ChB) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Transmit Message Buffer Slot Status Structure (ChAB) . . . . . . . . . . . . . . . . . . . . . . . . 148 Transmit Message Buffer Slot Status Structure (ChA) . . . . . . . . . . . . . . . . . . . . . . . . . 148 Transmit Message Buffer Slot Status Structure (ChB). . . . . . . . . . . . . . . . . . . . . . . . . . 148 Message Buffer Data Field Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Single Transmit Message Buffer Access Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Single Transmit Message Buffer States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Message Transmission Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Message Transmission from HLck state with unlock. . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Null Frame Transmission from Idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Null Frame Transmission from HLck state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Null Frame Transmission from HLck state with unlock . . . . . . . . . . . . . . . . . . . . . . . . 159 Null Frame Transmission from with locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Receive Message Buffer Access Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Receive Message Buffer States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Message Reception Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Double Transmit Buffer Structure and Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Double Transmit Message Buffer Access Regions Layout . . . . . . . . . . . . . . . . . . . . . . 168 Double Transmit Message Buffer State Diagram (Commit Side) . . . . . . . . . . . . . . . . . 170 Double Transmit Message Buffer State Diagram (Transmit Side). . . . . . . . . . . . . . . . . 171 Internal Message Transfer in Streaming Commit Mode . . . . . . . . . . . . . . . . . . . . . . . . 175 Internal Message Transfer in Immediate Commit Mode . . . . . . . . . . . . . . . . . . . . . . . . 175
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Freescale Semiconductor
Figure Number
Figure 3-127. Figure 3-128. Figure 3-129. Figure 3-130. Figure 3-131. Figure 3-132. Figure 3-133. Figure 3-134. Figure 3-135. Figure 3-136. Figure 3-137. Figure 3-138. Figure 3-139. Figure 3-140. Figure 3-141. Figure 3-142. Figure 3-143. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 5-1. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8.
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Inconsistent Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Message Buffer Reconfiguration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Received Frame FIFO Filter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Dual Channel Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Single Channel Device Mode (Channel A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Single Channel Device Mode (Channel B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 External Offset Correction Write and Application Timing . . . . . . . . . . . . . . . . . . . . . . 186 External Rate Correction Write and Application Timing . . . . . . . . . . . . . . . . . . . . . . . . 186 Sync Table Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Sync Frame Table Trigger and Generation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Strobe Signal Timing (type = pulse, clk_offset = -2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Strobe Signal Timing (type = pulse, clk_offset = +4) . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Slot Status Vector Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Slot Status Counting and SSCRn Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Scheme of cascaded interrupt request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 INT_CC# generation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Scheme of combined interrupt flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Part ID Register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 ASIC Version Number Register (AVNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Host Interface Pins Drive Strength Register (HIPDSR) . . . . . . . . . . . . . . . . . . . . . . . . . 208 Physical Layer Pins Drive Strength Register (PLPDSR) . . . . . . . . . . . . . . . . . . . . . . . . 209 Host Interface Pins Pullup/pulldown Enable Register (HIPPER) . . . . . . . . . . . . . . . . . 209 Host Interface Pins Pullup/pulldown Control Register (HIPPCR) . . . . . . . . . . . . . . . . . 211 Physical Layer Pins Pullup/pulldown Enable Register (PLPPER). . . . . . . . . . . . . . . . . 212 Physical Layer Pins Pullup/pulldown Control Register (PLPPCR) . . . . . . . . . . . . . . . . 213 VREG3V3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Detection Enable Register (DER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Clock and Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 CRG Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Clock Monitor Failure Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Interface Selection during Power-on or Low Voltage Reset or Clock Monitor Failure. 227 Interface Selection during External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 17
Figure Number
Figure 6-9. Figure 6-10. Figure 6-11. Figure A-1. Figure A-2. Figure A-3. Figure A-4. Figure A-5. Figure B-1. Figure B-2. Figure B-3. Figure C-1.
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CLKOUT Mode Selection and Control during Low-voltage Reset or Clock Monitor Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 CLKOUT Mode Selection and Control during External Reset . . . . . . . . . . . . . . . . . . . 230 CLKOUT Mode Selection and Control during Power-on Reset . . . . . . . . . . . . . . . . . . 231 Voltage Regulator -- Chip Power-up and Voltage Drops (not scaled) . . . . . . . . . . . . . 248 AMI Interface Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 AMI Interface Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 HCS12 Interface Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 HCS12 Interface Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 1) . . . . . . . . . . . . . . . . 255 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 2) . . . . . . . . . . . . . . . . 256 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 3) . . . . . . . . . . . . . . . . 257 Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode . . . . 260
MFR4300 Data Sheet, Rev. 3 18 Freescale Semiconductor
List of Tables
Table Number
Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21.
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Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Notational Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MFR4300 Device Memory Map After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Part ID and Module Version Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MFR4300 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CLKOUT Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Interface Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Recommended Pullup and Pulldown Resistor Values for IF_SEL[1:0] Inputs . . . . . . . . . 47 AMI Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HCS12 Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 List of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 External Signal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 FlexRay Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Register Access Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Additional Register Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Register Write Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MVR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Channel Enable Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STBSCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Strobe Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 STBPCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 MBDSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MBSSUTR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 POCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 GIFER Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PIFR0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PIFR1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PIER0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 PIER1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CHIERFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MFR4300 Data Sheet, Rev. 3
Freescale Semiconductor
19
Table Number
Table 3-22. Table 3-23. Table 3-24. Table 3-25. Table 3-26. Table 3-27. Table 3-28. Table 3-29. Table 3-30. Table 3-31. Table 3-32. Table 3-33. Table 3-34. Table 3-35. Table 3-36. Table 3-37. Table 3-38. Table 3-39. Table 3-40. Table 3-41. Table 3-42. Table 3-43. Table 3-44. Table 3-45. Table 3-46. Table 3-47. Table 3-48. Table 3-49. Table 3-50. Table 3-51. Table 3-52. Table 3-53. Table 3-54. Table 3-55. Table 3-56.
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MBIVEC Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CASERCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CBSERCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PSR0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PSR1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PSR2 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PSR3 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MTCTR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 CYCTR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SLTCTAR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SLTCTBR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 RTCORVR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 OFCORVR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 CIFRR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SFCNTR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SFTOR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SFTCCSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SFIDRFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SFIDAFVR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SFIDAFMR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 NMVR[0:5] Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Mapping of NMVRn to the Received Payload Bytes NMVn. . . . . . . . . . . . . . . . . . . . . . 102 NMVLR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 TICCR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TI1CYSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 TI1MTOR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 TI2CR0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 TI2CR1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SSSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Mapping Between SSSRn and SSRn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SSCCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Mapping between internal SSCCRn and SSCRn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SSR0-SSR7 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SSCR0-SSCR3 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 MTSACFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MFR4300 Data Sheet, Rev. 3
20
Freescale Semiconductor
Table Number
Table 3-57. Table 3-58. Table 3-59. Table 3-60. Table 3-61. Table 3-62. Table 3-63. Table 3-64. Table 3-65. Table 3-66. Table 3-67. Table 3-68. Table 3-69. Table 3-70. Table 3-71. Table 3-72. Table 3-73. Table 3-74. Table 3-75. Table 3-76. Table 3-77. Table 3-78. Table 3-79. Table 3-80. Table 3-81. Table 3-82. Table 3-83. Table 3-84. Table 3-85. Table 3-86. Table 3-87. Table 3-88. Table 3-89. Table 3-90. Table 3-91.
Title
Page
MTSBCFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 RSBIR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SEL Controlled Receiver FIFO Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 RFSR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 RFSIR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RFDSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RFARIR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RFBRIR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 RFMIDAFVR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RFMIAFMR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RFFIDRFVR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RFFIDRFMR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RFRFCFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RFRFCTR Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LDTXSLAR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LDTXSLBR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Protocol Configuration Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Wakeup Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 MBCCSRn Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 MBCCFRn Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Channel Assignment Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 MBFIDRn Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 MBIDXRn Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Frame Header Write Access Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Frame Header Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Receive Message Buffer Slot Status Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Receive Message Buffer Slot Status Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Transmit Message Buffer Slot Status Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Transmit Message Buffer Slot Status Structure Field Descriptions . . . . . . . . . . . . . . . . . 148 Message Buffer Data Field Minimum Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Frame Data Write Access Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Frame Data Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Individual Message Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Single Transmit Message Buffer Access Regions Description. . . . . . . . . . . . . . . . . . . . . 153 Single Transmit Message Buffer State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
MFR4300 Data Sheet, Rev. 3
Freescale Semiconductor
21
Table Number
Title
Page
Table 3-92. Single Transmit Message Buffer Application Transitions . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 3-93. Single Transmit Message Buffer Module Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 3-94. Single Transmit Message Buffer Transition Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 3-95. Receive Message Buffer Access Region Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 3-96. Receive Message Buffer States and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 3-97. Receive Message Buffer Application Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 3-98. Receive Message Buffer Module Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 3-99. Receive Message Buffer Transition Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 3-100. Receive Message Buffer Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 3-101. Double Transmit Message Buffer Access Regions Description . . . . . . . . . . . . . . . . . . . . 169 Table 3-102. Double Transmit Message Buffer State Description (Commit Side) . . . . . . . . . . . . . . . . 170 Table 3-103. Double Transmit Message Buffer State Description (Transmit Side) . . . . . . . . . . . . . . . 171 Table 3-104. Double Transmit Message Buffer Host Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 3-105. Double Transmit Message Buffer Module Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 3-106. Double Transmit Message Buffer Transition Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 3-107. Message Buffer Search Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 3-108. Sync Frame Table Generation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 3-109. Slot Status Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 3-110. Minimum CHI Frequency Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 3-111. Protocol Control Command Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 4-1. Pin Functions (Functional Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 4-2. Pin Functions (Reset Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 4-3. Port Integration Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 4-4. HIPDSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 4-5. PLPDSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 4-6. HIPPER Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 4-7. HIPPCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 4-8. PLPPER Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 4-9. PLPPCR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 5-1. VREG3V3V2 -- Signal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Table 5-2. VREG3V3V2 -- Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 6-1. MFR4300 Relevant Pins for the CRG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 6-2. DER Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 6-3. CRSR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 6-4. CRG Reset Sources Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
MFR4300 Data Sheet, Rev. 3 22 Freescale Semiconductor
Table Number
Table 6-5. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table C-1.
Title
Page
IF_SEL[1:0] Encoding by CRSR.ECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ESD and Latch-up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Thermal Package Simulation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5V I/O Characteristics (VDD5 = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 3.3V I/O Characteristics (VDD5 = 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Voltage Regulator -- Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Voltage Regulator Recommended Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 AMI Interface AC Switching Characteristics Over the Operating Range . . . . . . . . . . . . 252 HCS12 Interface AC Switching Characteristics Over the Operating Range . . . . . . . . . . 254 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 23
Table Number
Title
Page
MFR4300 Data Sheet, Rev. 3 24 Freescale Semiconductor
Chapter 1 Introduction
This data sheet provides information on a system that includes the MFR4300 FlexRay Communication Controller Module.
1.1
Audience
This data sheet is intended for application and system hardware developers who wish to develop products for the FlexRay MFR4300. It is assumed that the reader understands FlexRay protocol functionality and microcontroller system design.
1.2
Additional Reading
For additional reading that provides background to, or supplements, the information in this manual: * For more information about the FlexRay protocol, refer to the following document: -- FlexRay Communications System Protocol Specification V2.1 -- FlexRay Communications System Electrical Physical Layer Specification V2.1 * For more information about M9HCS12 Family devices and M9HCS12 programming, refer to the Freescale Products section at www.freescale.com.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 25
Introduction
1.3
Terminology
Table 1-1. Acronyms and Abbreviations
Term Meaning Asynchronous Memory Interface Buffer Control Unit Communication Controller Clock Domain Crosser Controller Host Interface Identification External Bus Interface FlexRay Memory Frame Start Sequence Host Interface Look Up Table Message Buffer Index Message Buffer Number Microcontroller Unit Microtick Macrotick Media Access Test Symbol Network Idle Time Protocol Engine Physical Layer Interface Physical Layer Protocol Operation Control Sequencer Engine Reception Time Control Unit Transmission
AMI BCU CC CDC CHI ID EBI FRM FSS HIF LUT MBIDX MBNum MCU T MT MTS NIT PE PHY PL POC SEQ Rx TCU Tx
MFR4300 Data Sheet, Rev. 3 26 Freescale Semiconductor
Introduction
Table 1-2. Notational Conventions
active-high active-low Names of signals that are active-high are shown in upper case text, without a `#' symbol at the end. Active-high signals are asserted (active) when they are high and deasserted when they are low. A `#' symbol at the end of a signal name indicates that the signal is active-low. An active-low signal is asserted (active) when it is at the logic low level and is deasserted when it is at the logic high level. A signal that is asserted is in its active logic state. An active-low signal changes from high to low when asserted; an active-high signal changes from low to high when asserted. A signal that is deasserted is in its inactive logic state. An active-low signal changes from low to high when deasserted; an active-high signal changes from high to low when deasserted. To set a bit means to establish logic level one on the bit. To clear a bit means to establish logic level zero on the bit. The prefix `0x' denotes a hexadecimal number. The prefix `0b' denotes a binary number. In certain contexts, such as a signal encoding, this indicates `don't care'. For example, if a field is binary encoded 0bx001, the state of the first bit is `don't care'. Used in equations, this symbol signifies comparison.
asserted deasserted set clear 0x0F 0b0011 x ==
1.4
Part Number Coding
Speed Option Package Option Temperature Option Device Title Controller Family Qualification P = Engineering Sample M = Qualified part 40 = 40 MHz AE = 64-pin Lead Free / Halide Free LQFP M = -40oC to +125oC
P FR 4300 M AE 40
Figure 1-1. Order Part Number Coding
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 27
Introduction
MFR4300 Data Sheet, Rev. 3 28 Freescale Semiconductor
Chapter 2 Device Overview
2.1 Introduction
The MFR4300 FlexRay Communication Controller implements the FlexRay protocol according to the FlexRay Communications System Protocol Specification V2.1. The controller host interface (CHI) of the MFR4300 FlexRay Communication Controller is implemented in accordance with Chapter 3, "FlexRay Module (FLEXRAYV2)" of this data sheet.
2.2
Features
The MFR4300 FlexRay controller provides the following features: * Single channel support -- Internal channel A and FlexRay Port A can be configured to be connected either to physical FlexRay channel A or physical FlexRay channel B * 128 configurable message buffers with -- Individual frame ID filtering -- Individual channel ID filtering -- Individual cycle counter filtering * Message buffer header, status and payload data are stored in FlexRay memory -- Consistent data access ensured by means of buffer locking scheme -- Host can lock multiple buffers at the same time * Size of message buffer data section configurable from 0 up to 254 bytes * Two independent message buffer segments with configurable size of payload data section -- Each segment can contain message buffers assigned to the static segment and message buffers assigned to the dynamic segment at the same time * Zero padding for transmit message buffers in static segment -- Applied when the frame payload length exceeds the size of the message buffer data section * Transmit message buffers configurable with state/event semantics * Message buffers can be configured as -- Receive message buffers -- Single buffered transmit message buffer -- Double buffered transmit message buffer (combines two single buffered message buffer) * Individual message buffer reconfiguration supported -- Means provided to safely disable individual message buffers -- Disabled message buffers can be reconfigured * Two independent receive FIFOs
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 29
Device Overview
* * *
* * * *
-- One receive FIFO per channel -- Up to 256 entries for each FIFO -- Global frame ID filtering, based on both value/mask filters and range filters -- Global channel ID filtering -- Global message ID filtering for the dynamic segment Four configurable slot error counters Four dedicated slot status indicators -- Used to observe slots without using receive message buffers Provides measured value indicators for clock synchronization -- PE internal synchronization frame ID and measurement tables can be copied into the FlexRay memory Fractional macroticks are supported for clock correction Maskable interrupt sources provided through individual and combined interrupt lines One absolute timer One timer that can be configured to absolute or relative
Features specific to the MFR4300 include the following: * Two hardware selectable host interfaces: -- HCS12 Interface for direct connection to Freescale's HCS12 family of microcontrollers, with interface clock signal to synchronize the data transfer (the maximum frequency of this clock signal can be calculated from the ECLK pulse width low and high times, tLEC and tHEC given in Table A-14.) -- Asynchronous Memory Interface (AMI) for asynchronous connection to microcontrollers -- minimum read access time of 53 ns (with CHICLK_CC running at 80 MHz) -- 8K bytes addressable for byte or word accesses * Internal quartz oscillator of 40 MHz * CHI and AMI clock selectable between 40 MHz oscillator clock used for PE and 20 MHz to 80 MHz separate CHI/AMI-only clock * Internal voltage regulator for the digital logic and the oscillator * Hardware selectable clock output to drive external host devices: disabled, 4, 10, or 40 MHz * Maskable interrupt sources available over one interrupt output line * Electrical physical layer interface compatible with dedicated FlexRay physical layer * Four multiplexed debug strobe pins
2.2.1
2.2.1.1
* *
MFR4300 Implementation Parameters and Constraints
Implementation Parameters
The duration of a microtick (T) is one CLK_CC period (25 ns at 40 MHz). A microtick starts with the rising edge of CLK_CC.
MFR4300 Data Sheet, Rev. 3
30
Freescale Semiconductor
Device Overview
2.2.1.2
* * *
Implementation Constraints
The external clock frequency for EXTAL/CLK_CC is 40 MHz. The minimum external clock frequency for CHICLK_CC (when selected) is 20 MHz. The maximum external clock frequency for CHICLK_CC is 80 MHz
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 31
Device Overview
2.3
Block Diagram
VDDR VSSR VDDA VSSA CHICLK_CC RESET# CLKOUT/TM0 D0/PA7 D1/PA6 D2/PA5 D3/PA4 D4/PA3 D5/PA2 D6/PA1 D7/PA0 D8/PB7 D9/PB6 D10/PB5 D11/PB4 D12/PB3 D13/PB2 D14/PB1 D15/PB0
VDD2_5 VSS2_5 XTAL EXTAL/CLK_CC VDDOSC VSSOSC A1/XADDR19 A2/XADDR18 A3/XADDR17 A4/XADDR16 A5/XADDR15 A6/XADDR14 A7 A8 A9 OE#/ACS0 A11/ACS1 A12/ACS2 WE#/RW_CC# CE#/LSTRB A10/ECLK_CC INT_CC# BSEL0#/DBG1 BSEL1#/DBG0 RXD_BG1 TXD_BG1/IF_SEL1 TXEN1#
Voltage Regulator
Oscillator
Clock and Reset Gen. Module External Clock Interface
AMI
HCS12 Interface
External Bus Interface
Receiver A
Receiver B
RXD_BG2 TXD_BG2/IF_SEL0 TXEN2#
Transmitter A
Transmitter B
TCU
Debug
DBG3/CLK_S1 DBG2/CLK_S0
FlexRay Module
TEST VDDX[1:4] VSSX[1:4]
Figure 2-1. MFR4300 Functional Block Diagram
MFR4300 Data Sheet, Rev. 3 32 Freescale Semiconductor
Device Overview
2.3.1
Memory Map
Table 2-1. MFR4300 Device Memory Map After Reset
Table 2-1 shows the MFR4300 device memory map.
address (Hex) 0x0000-0x000E 0x0010-0x0012 0x0014-0x0026 0x0028-0x003E 0x0040-0x0044 0x0046-0x004A 0x004C-0x0058 0x005A-0x0062 0x0064-0x0066 0x0068-0x007E 0x0080-0x0082 0x0084 0x0086-0x008A 0x008C-0x008E 0x0090-0x009A 0x009C, 0x009E 0x00A0-0x00DE 0x00E0-0x00E2 0x00E4-0x00EE 0x00F0-0x00FE 0x0100-0x01FE 0x0200-0x02FE 0x0300-0x03FE 0x0400-0x04FE 0x0500-0x07FE 0x0800-0x1FFE
1 2
Module FlexRay1 FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay CRG2 FlexRay PIM3 FlexRay FlexRay FlexRay FlexRay FlexRay FlexRay
Registers Configuration and Control Registers Reserved Interrupt and Error Handling Registers Protocol Status Registers Sync Frame Counter and Table Registers Sync Frame Filter Registers Network Management Vector Registers Timer Configuration Registers Slot Status Configuration Registers Slot Status and Slot Status Counter Registers MTS Generation Registers Shadow Buffer Configuration Register Receive FIFO -- Configuration Receive FIFO -- Status Receive FIFO -- Filter Dynamic Segment Status Registers Protocol Configuration Registers Clock and Reset Generation Registers Reserved Part ID, ASIC Version Number, and Interface Pin Drive Strength and Pullup/pulldown Control and Enable Registers Message Buffers Configuration, Control, Status (Message Buffer 0-31) Message Buffers Configuration, Control, Status (Message Buffer 32-63) Message Buffers Configuration, Control, Status (Message Buffer 64-95) Message Buffers Configuration, Control, Status (Message Buffer 96-127) Reserved Message Buffers and FIFO Frame Header/Offset/Status/Data
Size (bytes) 16 4 20 24 6 6 14 10 4 24 4 2 6 4 12 4 64 4 12 16 256 256 256 256 768 6144
For detailed information on the MFR4300 FlexRay module registers, see Chapter 3, "FlexRay Module (FLEXRAYV2)". For detailed information on the MFR4300 CRG module registers, see Chapter 6, "Clocks and Reset Generator (CRG)". 3 For detailed information on the MFR4300 PIM module registers, see Chapter 4, "Port Integration Module (PIM)".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 33
Device Overview
2.3.2
Part ID and Module Version Number Assignments
Three 16-bit read-only registers provide information about the device and the MFR4300 FlexRay module (see Table 2-2).
Table 2-2. Part ID and Module Version Numbers
Part ID Device Mask Set Number PIDR MFR4300 0M92D 4300 AVNR 0000 MVR 3535
The PIDR (see Section 4.3.1.1, "Part ID Register (PIDR)") provides the part ID number in binary coded decimal (in this case, `4300') The AVNR (see Section 4.3.1.2, "ASIC Version Number Register (AVNR)") provides the asic version number in binary coded decimal (in this case, `0000'). The MVR (see Section 3.3.2.3, "Module Version Register (MVR)") provides the FlexRay module version number in binary coded decimal (in this case, `3535'). Bits 15 to 8 of the MVR comprise the controller host interface (CHI) version number; bits 7 to 0 comprise the protocol engine (PE) version number. These read-only values provide a unique ID for each revision of the device.
2.4
2.4.1
Signal Descriptions
System Pinout
The MFR4300 is available in a 64-pin low profile quad flat package (LQFP). Most pins perform two functions, as described in Section 2.4.2, "Pin Functions and Signal Properties". Figure 2-2 shows the pin assignments. NOTE For a recommended printed circuit board layout, see Appendix C, "Printed Circuit Board Layout Recommendations".
MFR4300 Data Sheet, Rev. 3 34 Freescale Semiconductor
Device Overview
Figure 2-2. MFR4300 Pin Assignment
Freescale Semiconductor
VSSR VDDR A8 A9 VSSOSC EXTAL/CLK_CC XTAL VDDOSC OE#/ACS0 A11/ACS1 CE#/LSTRB WE#/RW_CC# VSSX4 CHICLK_CC
A6/XADDR14 A7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TEST D9/PB6 D10/PB5 D11/PB4 D12/PB3 D13/PB2 D14/PB1 VDDX1 VSSX1 D15/PB0 A1/XADDR19 A2/XADDR18 A3/XADDR17 A4/XADDR16 A5/XADDR15 RESET#
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
D8/PB7 D7/PA0 VSS2_5 VDD2_5 D6/PA1 D5/PA2 D4/PA3 D3/PA4 VDDX3 VSSX3 A10/ECLK_CC D2/PA5 VDDA VSSA
INT_CC#
CLKOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
BSEL1#/DBG0 BSEL0#/DBG1 DBG3/CLK_S1 TXD_BG2/IF_SEL0 TXEN2# RXD_BG2 DBG2/CLK_S0 TXD_BG1/IF_SEL1 D1/PA6 D0/PA7 VSSX2 VDDX2 TXEN1# VDDX4 A12/ACS2 RXD_BG1
MFR4300 Data Sheet, Rev. 3 35
Device Overview
2.4.2
Pin Functions and Signal Properties
Table 2-3. Pin Functions and Signal Properties
Pin Name1
Pin #
Function 1
Function 2
Powered I/O by
Pin Type2, 3
Reset
Functional Description
Host Interface Pins 11 A1 XADDR19 VDDX I PC AMI address bus / HCS12 expanded address lines. A1-LSB of the AMI address bus, XADDR14-LSB of the HCS12 expanded address lines AMI address bus / HCS12 expanded address lines. AMI address bus / HCS12 expanded address lines. AMI address bus / HCS12 expanded address lines. AMI address bus / HCS12 expanded address lines. AMI address bus / HCS12 expanded address lines. AMI address bus AMI address bus AMI address bus AMI read output enable signal / HCS12 address select input AMI address bus / HCS12 address select inputs AMI address bus / HCS12 address select inputs AMI byte select / Debug strobe point AMI byte select / Debug strobe point AMI data bus / HCS12 multiplexed address/data bus. D15 is the MSB of the AMI data bus, PB0 is the LSB of the HCS12 address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus. AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus
12 13 14 15 17 18 21 22 27 28 34 48 47 10
A2 A3 A4 A5 A6 A7 A8 A9 OE# A11 A12 BSEL1# BSEL0# D15
XADDR18 XADDR17 XADDR16 XADDR15 XADDR14 ACS0 ACS1 ACS2 DBG0 DBG1 PB0
VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
I I I I I I I I I I I I/O I/O I/O
PC PC PC PC PC PC PC PC PC PC PC PC PC Z/DC/PC
Z
7 6 5 4 3 2 62 61 58 57 56
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3
VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC
Z Z Z Z Z Z Z Z Z Z Z
MFR4300 Data Sheet, Rev. 3 36 Freescale Semiconductor
Device Overview
Table 2-3. Pin Functions and Signal Properties (Continued)
Pin # 55 51 40 39 Pin Name1 Function 1 D3 D2 D1 D0 Function 2 PA4 PA5 PA6 PA7 Powered I/O by VDDX VDDX VDDX VDDX I/O I/O I/O I/O Pin Type2, 3 Z/DC/PC Z/DC/PC Z/DC/PC Z/DC/PC Reset Functional Description
Z Z Z Z
AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus AMI data bus / HCS12 multiplexed address/data bus. D0 is the LSB of the AMI data bus, PA7 is the MSB of the HCS12 address/data bus AMI chip select signal / HCS12 low-byte strobe signal AMI write enable signal/ HCS12 read/write select signal AMI address bus/ HCS12 clock input
29 30 52
CE# WE# A10
LSTRB RW_CC# ECLK_CC
VDDX VDDX VDDX
I I I
PC PC PC
-
Physical Layer Interface 33 43 36 44 45 41 RXD_BG1 RXD_BG2 TXEN1# TXEN2# TXD_BG2 TXD_BG1 IF_SEL0 IF_SEL1 VDDX VDDX VDDX VDDX VDDX VDDX I I O O I/O I/O PC PC DC DC DC/PD DC/PD 1 1 PHY Data receiver input PHY Data receiver input Transmit enable for PHY Transmit enable for PHY PHY Data transmitter output / Host interface select PHY Data transmitter output / Host interface select
Clock Signals 32 63 CHICLK_CC CLKOUT VDDX VDDX I I/O DC External CHI clock input - selectable Controller clock output - selectable as disabled/4/10/40 MHz
Others 16 64 1 42 46 RESET# INT_CC# TEST DBG2 DBG3 CLK_S0 CLK_S1 VDDX VDDX VDDX VDDX VDDX I O I I/O I/O OD/DC PD DC/PD DC/PD 0 External hardware reset input Controller interrupt output Factory Test mode select - must be tied to logic low in application Debug strobe point / Output clock select Debug strobe point / Output clock select
Oscillator 24 25 EXTAL XTAL CLK_CC VDDOSC I I Crystal driver / External clock Crystal driver
Supply/Bypass Filter pins 8 VDDX1 Supply voltage, I/O
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 37
Device Overview
Table 2-3. Pin Functions and Signal Properties (Continued)
Pin # 37 54 35 9 38 53 31 20 19 50 49 59 60 26 23
1 2
Pin Name1 Function 1 VDDX2 VDDX3 VDDX4 VSSX1 VSSX2 VSSX3 VSSX4 VDDR VSSR VDDA VSSA VDD2_54 VSS2_54 VDDOSC4 VSSOSC4 Function 2
Powered I/O by -
Pin Type2, 3 -
Reset
Functional Description
-
Supply voltage, I/O Supply voltage, I/O Supply voltage, I/O Supply voltage ground, I/O Supply voltage ground, I/O Supply voltage ground, I/O Supply voltage ground, I/O Supply voltage, supply to pin drivers and internal Voltage Regulator Supply voltage ground, ground to pin drivers and internal Voltage Regulator Supply analog voltage Supply analog voltage ground Core voltage power supply output (nominally 2.5V) Core voltage ground output Oscillator voltage power supply output (nominally 2.5V) Oscillator voltage ground output
# - signal is active-low Acronyms: PC - (Pullup/pulldown Controlled) Register controlled internal weak pullup/pulldown for a pin in the input mode. Refer to the following sections for more information: - Section 4.3.1.5, "Host Interface Pins Pullup/pulldown Enable Register (HIPPER)" - Section 4.3.1.6, "Host Interface Pins Pullup/pulldown Control Register (HIPPCR)" - Section 4.3.1.7, "Physical Layer Pins Pullup/pulldown Enable Register (PLPPER)" - Section 4.3.1.8, "Physical Layer Pins Pullup/pulldown Control Register (PLPPCR)" PD - (Pulldown) Internal weak pulldown for a pin in the input mode DC - (Drive strength Controlled) Register controlled drive strength for a pin in the output mode. Refer to the following sections for more information: - Section 4.3.1.3, "Host Interface Pins Drive Strength Register (HIPDSR)" - Section 4.3.1.4, "Physical Layer Pins Drive Strength Register (PLPDSR)" Z - Tristated pin OD - (Open Drain) Output pin with open drain 3 Reset state: All pins with the PC option - pullup/pulldown is disabled, all pins with the DC option - have full drive strength 4 No load allowed except for bypass capacitors.
MFR4300 Data Sheet, Rev. 3 38 Freescale Semiconductor
Device Overview
2.4.3
2.4.3.1
Detailed Signal Descriptions
A[6:1]/XADDR[14:19] -- AMI Address Bus, HCS12 Expanded Address Inputs
A[6:1]/XADDR[14:19] are general purpose input pins. Their function is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. (See Section 4.3.1.5, "Host Interface Pins Pullup/pulldown Enable Register (HIPPER)" and Section 4.3.1.6, "Host Interface Pins Pullup/pulldown Control Register (HIPPCR)".) A[6:1] are AMI interface address signals. A1 is the LSB of the AMI address bus. XADDR[14:19] are HCS12 interface expanded address lines. XADDR14 is the LSB of the HCS12 interface expanded address lines.
2.4.3.2
A[9:7] -- AMI Address Bus
A[9:7] are general purpose input pins. Their function is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. A[9:7] are AMI interface address signals.
2.4.3.3
OE#/ACS0 -- AMI Read Output Enable, HCS12 Address Select Input
OE#/ACS0 is a general purpose input pin. Its function is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. OE# is the AMI interface output enable signal. This signal controls MFR4300 data output and the state of three-stated data pins D[15:0] during host read operations. ACS0 is an HCS12 interface address select signal.
2.4.3.4
A[12:11]/ACS[2:1] -- AMI Address Bus, HCS12 Expanded Address Inputs
A[12:11]/ACS[2:1] are general purpose input pins. Their function is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. A[12:11] are AMI interface address signals. ACS[1:2] are HCS12 interface address select signals.
2.4.3.5
BSEL[1:0]#/DBG[0:1] -- AMI Byte Select, Debug Strobe Points
BSEL[1:0]#/DBG[0:1] are general purpose input or output pins. Their function is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pins can be
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 39
Device Overview
configured to provide either high or reduced output drive, and also to enable or disable either pullup or pulldown resistors on the pins. BSEL[1:0]# are AMI byte select signals. DBG[0:1] are debug strobe point output signals. The functions output on these pins are selected by the debug port control register. Refer to Section 3.4.16, "Strobe Signal Support" for more information.
2.4.3.6
D[15:8]/PB[0:7] -- AMI Data Bus, HCS12 Multiplexed Address/Data Bus
D[15:8]/PB[0:7] are general purpose input or output pins. Their functions are selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. These pins can be configured to provide either high or reduced output drive, and also to enable or disable either pullup or pulldown resistors on the pins. D[15:8] are data signals of the AMI interface. D15 is the MSB of the AMI data bus. PB[0:7] are HCS12 interface multiplexed address/data signals in the HCS12 Host interface mode of operation. PB0 is the LSB of the HCS12 address/data bus.
2.4.3.7
D[7:0]/PA[0:7] -- AMI Data Bus, HCS12 Multiplexed Address/Data Bus
D[7:0]/PA[0:7] are general purpose input or output pins. Their functions are selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. These pins can be configured to provide either high or reduced output drive, and also to enable or disable either pullup or pulldown resistors on the pins. D[7:0] are data signals of the AMI interface. D0 is the LSB of the AMI data bus. PA[0:7] are HCS12 interface multiplexed address/data signals in the HCS12 Host interface mode of operation. PA7 is the MSB of the HCS12 address/data bus.
2.4.3.8
CE#/LSTRB -- AMI Chip Select, HCS12 Low-byte Strobe
The function of this pin is selected by IF_SEL[1:0] pins. Refer Section 2.7, "External Host Interface" for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. CE# is an AMI interface transfer size input signal. It indicates the size of the requested data transfer in the current bus cycle. LSTRB is an HCS12 interface low-byte strobe input signal. It indicates the type of bus access.
2.4.3.9
WE#/RW_CC# -- AMI Write Enable, HCS12 Read/Write Select
The function of this pin is selected by the IF_SEL[1:0] pins. Refer to Section 2.7, "External Host Interface" for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. WE# is an AMI interface write select signal. It strobes the valid data provided by the host on the D[15:0] pins during write operations to the MFR4300 memory.
MFR4300 Data Sheet, Rev. 3 40 Freescale Semiconductor
Device Overview
RW_CC# is an HCS12 interface read/write input signal. It indicates the direction of data transfer for a transaction.
2.4.3.10
A10/ECLK_CC -- AMI Address Bus, HCS12 Clock Input
The function of this pin is selected by the IF_SEL[1:0] pins. Refer Section 2.7, "External Host Interface" for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. A10 is an AMI interface address signal. ECLK_CC is the HCS12 interface clock input signal. (The maximum frequency of this signal can be calculated from the ECLK pulse width low and high times, tLEC and tHEC given in Table A-14.)
2.4.3.11
RXD_BG[2:1] -- PHY Data Receiver Inputs
RXD_BG[2:1] are bus driver receive data input signals if the FlexRay Optical/Electrical PHY is configured: * RXD_BG1 is the input to the CC from Physical Layer Channel 1 * RXD_BG2 is the input to the CC from Physical Layer Channel 2 These pins can be configured to enable or disable either pullup or pulldown resistors on the pins.
2.4.3.12
TXEN[2:1]# -- PHY Transmit Enable
TXEN[2:1]# are bus driver transmit enable output signals if the FlexRay Optical/Electrical PHY is configured: * TXEN1# is the output of the CC to Physical Layer Channel 1 * TXEN2# is the output of the CC to Physical Layer Channel 2 These pins can be configured to provide either high or reduced output drive.
2.4.3.13
TXD_BG[1:2]/IF_SEL[1:0] -- PHY Transmit Data Outputs, Host Interface Selection
These pins can be configured to provide either high or reduced output drive. TXD_BG[1:2] are bus driver transmit data output signals if the FlexRay Optical/Electrical PHY is configured: * TXD_BG1 is the output of the CC to Physical Layer Channel 1 * TXD_BG2 is the output of the CC to Physical Layer Channel 2 IF_SEL[1:0] are the CC external interface selection input signals. Refer to Table 2-6 for the selection coding. NOTE The IF_SEL[1:0] signals are inputs during the internal reset sequence and are latched during the internal reset sequence.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 41
Device Overview
While the IF_SEL[1:0] levels are being latched, the output drive control is disabled, and the internal pulldown resistors are connected to the pins. As IF_SEL[1:0] signals share pins with Physical Layer Interface signals, pullup/pulldown devices must be used for the selection. Recommended pullup/pulldown resistor values for the IF_SEL[1:0] inputs are given in Section 2.6.3, "Recommended Pullup/pulldown Resistor Values".
2.4.3.14
CHICLK_CC -- External CHI Clock Input
CHICLK_CC is the selectable external CHI clock input. It can be selected to drive the Asynchronous Memory Interface (see Section 2.6.2, "External Host Interface Selection").
2.4.3.15
CLKOUT -- Clock Output
CLKOUT is a continuous clock output signal. The frequency of CLKOUT is selected by the CLK_S[1:0] pins. The CLKOUT signal, if enabled, is always active: 1. after power-up of the CC, 2. after a low-voltage reset, 3. after a clock monitor failure reset, 4. during and after an external hard reset. The pin can be configured to provide either high or reduced output drive. NOTE As the CLKOUT signal can be disabled during internal resets, refer to Section 6.4.3, "CLKOUT Mode Selection and Control" for more information on CLKOUT generation during external hard and internal resets.
2.4.3.16
RESET# -- External Reset
RESET# is an active-low control signal that acts as an input to initialize the CC to a known startup state.
2.4.3.17
INT_CC# -- Interrupt Output
INT_CC# is an AMI and HCS12 interfaces interrupt request output signal. The CC may request a service routine from the host to run. The interrupt is indicated by the logic level: the interrupt is asserted if the INT_CC# outputs a logic 0 and is deasserted if INT_CC# outputs a logic 1. The pin can be configured to provide either high or reduced output drive. This is an open-drain output.
2.4.3.18
TEST
The TEST pin is pulled down, internally, and must be tied to VSS in all applications.
MFR4300 Data Sheet, Rev. 3 42 Freescale Semiconductor
Device Overview
2.4.3.19
DBG[3:2]/CLK_S[1:0] -- Debug Strobe Points, Output Clock Select
DBG[3:2] are debug strobe point output signals. The functions output on these pins are selected by the debug port control register. Refer to Section 3.4.16, "Strobe Signal Support" for more information. NOTE CLK_S[1:0] signals are inputs during the internal reset sequence and are latched during the internal reset sequence. While the CLK_S[1:0] levels are being latched, the output drive control is disabled, and the internal pulldown resistors are connected to the pins.
2.4.3.20
EXTAL/CC_CLK -- Crystal Driver, External Clock Pin
This pin can act as a crystal driver pin (EXTAL) or as an external clock input pin (CC_CLK). On reset, the device clock is derived from the input frequency on this pin. Refer to Figure 2-3 for Pierce oscillator connections and Figure 2-4 for external clock connections. See also Chapter 7, "Oscillator (OSCV2)".
2.4.3.21
XTAL -- Crystal Driver Pin
XTAL is a crystal driver pin. Refer to Figure 2-3 for oscillator connections and Figure 2-4 for external clock connections. See also Chapter 7, "Oscillator (OSCV2)".
MFR4300
EXTAL Q Rb Rs XTAL VDDOSC C3 VSSOSC VSSOSC VSSOSC C2
C1 Where: * Q = 40 MHz crystal * Rb is in the range 1M - 10 M * Rs is a lower value, which can be 0 * C1 = C2 * See crystal manufacturer's product specification for recommended values Oscillator supply output capacitor C3 = 220 nF
Figure 2-3. Oscillator Connections
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 43
Device Overview
MFR4300
EXTAL
G CLKOUT
XTAL VDDOSC
Not connected (left open) C3
Where: G = 40 MHz CMOS-compatible External Oscillator (VDDOSC-Level)
VSSOSC VSSOSC
Figure 2-4. External Square Wave Clock Generator Connection
2.4.4
Power Supply Pins
NOTE All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MFR4300 as possible. Bypass requirements depend on how heavily the MFR4300 pins are loaded.
Table 2-4. MFR4300 Power and Ground Connection Summary
Pin Number
MFR4300 power and ground pins are summarized in Table 2-4 and described below.
Mnemonic 64-pin LQFP VDD2_5 VSS2_5 VDDR VSSR VDDX[1:4] VSSX[1:4] VDDA VSSA VDDOSC VSSOSC 59 60 20 19 8, 37, 54, 35 9, 38, 53, 31 50 49 26 23
Nominal Voltage 2.5V 0V 3.3V 0V 3.3V 0V 3.3V 0V 2.5V 0V
Description
Internal power and ground generated by internal regulator
External power and ground, supply to supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers.
Operating voltage and ground for the internal voltage regulator.
Provides operating voltage and ground for the internal oscillator. This allows the supply voltage to the oscillator to be bypassed independently. Internal power and ground generated by internal regulator.
MFR4300 Data Sheet, Rev. 3 44 Freescale Semiconductor
Device Overview
2.4.4.1
VDDX, VSSX -- Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers.
2.4.4.2
VDDR, VSSR -- Power and Ground Pins for I/O Drivers and Internal Voltage Regulator
NOTE The VDDR pin enables the internal 3.3 V to 2.5 V voltage regulator. If this pin is tied to ground, the internal voltage regulator is turned off.
External power and ground for I/O drivers and input to the internal voltage regulator.
2.4.4.3
VDD2_5, VSS2_5 -- Core Power Pins
Power is supplied to the MFR4300 core through VDD2_5 and VSS2_5. This 2.5 V supply is derived from the internal voltage regulator. No static load is allowed on these pins. If VDDR is tied to ground, the internal voltage regulator is turned off. NOTE No load is allowed except for bypass capacitors.
2.4.4.4
VDDA, VSSA -- Power Supply Pins for VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator. They also provide the reference voltages for the internal voltage regulator.
2.4.4.5
VDDOSC, VSSOSC -- Power Supply Pins for OSC
VDDOSC, VSSOSC provide operating voltage and ground for the oscillator. This allows the supply voltage to the oscillator to be bypassed independently. This 2.5 V voltage is generated by the internal voltage regulator. NOTE No load is allowed except for bypass capacitors.
2.5
Modes of Operation
Refer to Section 3.1.6, "Modes of Operation" for full descriptions of the MFR4300 Disabled and Normal modes of operation.
2.6
2.6.1
External Clock and Host Interface Selection
External 4/10/40 MHz Output Clock
A continuous external 4/10/40 MHz output clock signal is provided by the CC on the CLKOUT pin. See Section 2.4.3.15, "CLKOUT -- Clock Output" for details of when this signal is active.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 45
Device Overview
The output frequency of the CLKOUT signal is selected by the CLK_S[1:0] input pins, in accordance with Table 2-5:
Table 2-5. CLKOUT Frequency Selection
Pin CLKOUT Function CLK_S0 0 1 0 1 CLK_S1 0 0 1 1 4 MHz output 10 MHz output 40 MHz output Disabled (CLKOUT output is "0")
NOTE As the CLK_S[1:0] signals are multiplexed with DBG[2:3], CLKOUT should be selected using pullup and pulldown resistors
2.6.2
External Host Interface Selection
The MFR4300 can be connected and controlled by two types of interface through the CC EBI. Two pins, IF_SEL0 and IF_SEL1, are used to configure the interface type, in accordance with Table 2-6.
Table 2-6. Interface Selection
Pin Interface IF_SEL0 0 0 1 1 IF_SEL1 0 1 0 1 Reserved HCS12 Synchronous Interface Asynchronous Memory Interface Asynchronous Memory Interface CHI and Host Interface Clock CLK_CC CLK_CC CLK_CC CHICLK_CC
The CC latches the values of the IF_SEL0 and IF_SEL1 signals, when it leaves an internal or external reset state, and analyzes them in order to configure the interface for the type of external host. The CC does not analyze them after it has left the reset state. For more information on the internal and external reset states, see Chapter 6, "Clocks and Reset Generator (CRG)". NOTE If the CC senses the Reserved mode on its IF_SEL pins (IF_SEL[1:0] = 00), it stops all internal operations, does not perform or respond to any host transactions, stays in the configuration mode, and does not integrate into the communication process. The following steps must be taken to select a correct external host interface mode: 1.Set IF_SEL0, IF_SEL1 for either the AMI or the HCS12 synchronous mode.
MFR4300 Data Sheet, Rev. 3 46 Freescale Semiconductor
Device Overview
2.Assert the external hard reset signal of the CC again.
2.6.3
Recommended Pullup/pulldown Resistor Values
As the IF_SEL[1:0] signals share pins with Physical Layer Interface signals, pullup and pulldown resistors should be used for the selection. The recommended pullup/pulldown resistor values for the IF_SEL[1:0] inputs are given in Table 2-7:
Table 2-7. Recommended Pullup and Pulldown Resistor Values for IF_SEL[1:0] Inputs
IO, Regulator and analog supply level (VDD5) 3.3V 5V
1
Pullup resistor1 16 10
Pulldown resistor1 47 47
Units k k
The listed values are calculated for the MFR4300-Physical Layer connection where no internal pullup/pulldown resistors are assumed in the Electrical PHY at the TXD_BG1 and TXD_BG2 interface lines. If an Electrical PHY device has internal pullup/pulldown resistors connected to these signals, then the external pullup/pulldown resistor values must be recalculated to ensure that VIL requirements for pulldown resistors or VIH requirements for pullup resistors for the chosen VDD5 are met. See Section A.1.9, "I/O Characteristics" for more details on VIL, VIH and VDD5.
2.7
External Host Interface
The MFR4300 can be connected through two types of bus interface (see Section 2.6.2, "External Host Interface Selection" for information on how to select the host interface). The two types of microprocessor interface are described below.
2.7.1
Asynchronous Memory Interface
Figure 2-5 shows how to connect the FlexRay CC to a microcontroller using the AMI interface. * Data exchange in AMI Mode is controlled by the CE#, WE# and OE# signals. * The FlexRay AMI interface is implemented as an asynchronous memory slave module, thus enabling fast interfacing between the CC and a variety of microcontrollers. * The FlexRay CC MCU interface decodes its internal register addresses with the help of the chip select signal CE# and the address lines A[12:1]. * The AMI interface accepts only aligned 16-bit read and 8-bit or 16-bit write transactions. The AMI interface does not support 8-bit read accesses. -- The byte selects BSEL[1:0]#, the chip enable CE#, the output enable OE#, and the write enable WE# are used to determine the type of access as shown in Table 2-8.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 47
Device Overview
Table 2-8. AMI Access Types
CE# 0 0 0 0 0 0 0 1
1 2
WE# 0 0 0 0 0 1 1 X
OE# 0 1 1 1 1 1 0 X
BSEL1# X 0 0 1 1 X X X
BSEL0# X 0 1 0 1 X X X Illegal
Type of Access
16-bit write to word address1 8-bit write to even byte address2 8-bit write to odd byte address3 Illegal no access 16-bit read from word address4 no access
Write data from D[15:8] to even byte address and from D[7:0] to odd byte address. Write data from D[15:8]. 3 Write data from D[7:0]. 4 Read data from even byte address at D[15:8] and from odd byte address at D[7:0].
* * * *
WE# indicates the direction of data transfer for a transaction. OE# enables the AMI data output to a microcontroller during read transactions. INT_CC# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from a host controller. The FlexRay CC AMI module does not support burst transactions. NOTE For the AMI, D0 is the LSB of the 16-bit data bus. NOTE If the AMI mode without the CHICLK_CC signal is selected (i.e. IF_SEL[1:0] = 0b01), CHICLK_CC must be driven to logic 0 or logic 1 (it must not be left floating).
MFR4300 Data Sheet, Rev. 3 48 Freescale Semiconductor
Device Overview
2.7.1.1
Asynchronous Memory Interface with MPC5xx and MPC55xx Families
MPC5xx Family MPC55xx Family DATA0
MFR4300
D15 ... D0 A12 ... A1 BSEL1# BSEL0# WE# CE# OE# VDDXn
... DATA15
ADDR19 ... ADDR30 BE0 BE1 WE# CSn# OE#
IRQn# PL Interface
INT_CC# TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1
VSSXn
Figure 2-5. AMI Interface with MPC5xx and MPC55xx Families
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 49
Device Overview
2.7.1.2
Asynchronous Memory Interface with S12X Family
S12X Family
D15 ... D0 A12 ... A1 UDS LDS CSn WE RE D15 ... D0 A12 ... A1 BSEL1# BSEL0# CE# WE# OE#
MFR4300
VDDXn
IRQn PL Interface
INT_CC# TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1
VSSXn
Figure 2-6. AMI Interface with S12X Family
MFR4300 Data Sheet, Rev. 3 50 Freescale Semiconductor
Device Overview
2.7.1.3
Asynchronous Memory Interface with DSP 56F83 (Hawk) Family
MFR4300
D15 ... D0 A11 ... A0 D15 ... D0 A12 ... A1
DSP56F83xx Family
WR# CSn# RD# VDDXn
WE# CE# OE# BSEL1# BSEL0#
IRQn# PL Interface
INT_CC# TXD_BG2/IF_SEL0 TXD_BG1/IF_SEL1
VSSXn
Figure 2-7. AMI Interface with DSP 56F83 (Hawk) Family
2.7.1.4
Asynchronous Memory Interface Timing
See Section A.4, "Asynchronous Memory Interface Timing" for timing characteristics of the CC AMI Interface.
2.7.2
HCS12 Interface
Chip selection for the HCS12 interface is generated internally using the following signals (see Figure 2-8): * The input values of the expanded address signals XADDR[14:19] are compared with logical 0's (the HCS12 External Bus Interface (EBI) is in the Paged or Unpaged mode). * The three most significant bits of the demultiplexed address bus, PA[5:7], are compared with the pattern set up externally on the address chip select pins ACS[0:2]; PA5 is compared with ACS0, PA6 with ACS1, PA7 with ACS2. NOTE The address decoding phase of a read/write operation is passed if all the comparisons described above are passed.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 51
Device Overview
Figure 2-9 shows how to connect the FlexRay CC to an HCS12 MCU with EBI paged mode support. Figure 2-10 shows how to connect he FlexRay CC to an HCS12 MCU with EBI unpaged mode support. * The CC's HCS12 interface supports the paged and the unpaged modes of the HCS12 External Bus Interface connected to it. * The FlexRay HCS12 interface is implemented as an synchronous HCS12 External Bus slave module, thus enabling the fast data exchange between them. * The FlexRay CC MCU interface decodes the addresses of read/write transactions to its internal registers, and generates its internal chip select signal, CS, using the address/data lines PA[0:7], PB[0:7], ACS[0:2], and XADDR[14:19]: -- The address and data lines PA[0:7], PB[0:7] are multiplexed. They are denoted ADR[0:15] when referring to the address, and DATA[0:15] when referring to the data. The FlexRay CC is selected only when the address ADR[13:15] matches ACS[0:2] (ADR13 matches ACS0, ADR12 matches ACS1, etc.) and the address XADDR[14:19] matches 0. * The HCS12 interface accepts only aligned 16-bit read and 8-bit or 16-bit write transactions. The HCS12 interface does not support 8-bit read accesses. -- The internal chip select, CS, the low byte strobe, LSTRB, the least significant bit of the address, ADR0, and the read/write select, RW, are used to determine the type of access, as shown in Table 2-9.
Table 2-9. HCS12 Access Types
CS 0 1 1 1 1 1 1 1 1
1 2
RW X 0 0 0 0 1 1 1 1
LSTRB X 0 0 1 1 0 0 1 1
ADR0 X 0 1 0 1 0 1 0 1 No access
Type of Access
16-bit write to word address1 8-bit write to an odd address2 8-bit write to an even address2 Not supported 16-bit read from an even address3 Not supported Not supported Not supported
Write data from PA to even byte address and from PB to odd byte address. Write data from PB. 3 Read data from even byte address at PA and from odd byte address at PB.
* *
RW_CC# indicates the direction of data transfer for a transaction. INT_CC# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from the HCS12 device.
MFR4300 Data Sheet, Rev. 3 52 Freescale Semiconductor
Device Overview
NOTE AMI-only inputs A[9:7], BSEL[1:0]#/DBG[0:1] (if the debug strobes are disabled), and CHICLK_CC are not used when the HCS12 interface is selected and must be driven to logic 0 or logic 1 (i.e. they must not be left floating).
PA[0:7] PB[0:7]
16 bit
Address /Data Delimitplexer
16 bit
DATA[0:15] DATA SIGNALS ADR[0:15] ADDRESS SIGNALS
16 bit
10 bit ADR[13:15] 3 bit ACS[0:2] ACS[0:2] 3 bit
ADR[0:9] ADDRESS SIGNALS Address Comparator 1 & CS
XADDR[14:19] XADDR[14:19] 6 bit
Address Comparator 2 1
`000000'
6 bit 1 0
ADR[14:15] 2 bit `01' 2 bit
Address Comparator 3
Figure 2-8. HCS12 Interface Address Decoding and Internal Chip Select Generation
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 53
Device Overview
2.7.2.1
HCS12 interface with HCS12 Page Mode Support
HCS12 family ADDR/DATA15 (PA7) ... ADDR/DATA0 (PB0) XADDR19 ... XADDR14 ECLK LSTRB R/W# VDDXn PA7 ... PB0 XADDR19 ... XADDR14 ECLK_CC LSTRB RW_CC#
MFR4300
ACS2 ACS1 ACS0
IRQn# PL Interface
INT_CC# TXD_BG1/IF_SEL1 TXD_BG2/IF_SEL0
VSSXn
Figure 2-9. HCS12 interface with HCS12 Page Mode Support
MFR4300 Data Sheet, Rev. 3 54 Freescale Semiconductor
Device Overview
2.7.2.2
HCS12 interface with HCS12 Unpaged Mode Support
MFR4300
PA7 ... PB0 6 VSSXn ECLK LSTRB R/W# VDDXn XADDR19 ... XADDR14 ECLK_CC LSTRB RW_CC#
HCS12 Family
ADDR/DATA15 (PA7) ... ADDR/DATA0 (PB0)
ACS2 ACS1 ACS0
IRQn# PL Interface
INT_CC# TXD_BG1/IF_SEL1 TXD_BG2/IF_SEL0
VSSXn
Figure 2-10. HCS12 interface with HCS12 Unpaged Mode Support
2.7.2.3
HCS12 Interface Timing
See Section A.5, "HCS12 Interface Timing" for timing characteristics of the HCS12 interface.
2.8
2.8.1
Resets and Interrupts
Resets
MFR4300 has the following resets: * External hard reset input signal RESET#.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 55
Device Overview
*
*
Internal power-on and low-voltage resets provided by the internal voltage regulator (refer to Chapter 6, "Clocks and Reset Generator (CRG)" and Chapter 5, "Dual Output Voltage Regulator (VREG3V3V2)" for more information). Internal clock monitor failure reset (see Chapter 7, "Oscillator (OSCV2)").
When a reset occurs, MFR4300 registers and control bits are changed to known startup states. Refer to the respective module chapters for information on the different kinds of resets and for register reset states.
2.8.1.1
I/O Pin States After Reset
Refer to Table 2-3 for the configuration of the MFR4300 pins out of reset.
2.8.2
Interrupt Sources
All possible MFR4300 internal interrupt sources are combined and provided to the host by means of one available interrupt line, INT_CC#. Refer to Section 3.4.19, "Interrupt Support" and Section 6.3.2, "Clock and Reset Status Register (CRSR)" for more information on available interrupt sources. The type of interrupt is level sensitive.
MFR4300 Data Sheet, Rev. 3 56 Freescale Semiconductor
Chapter 3 FlexRay Module (FLEXRAYV2)
3.1
3.1.1
Introduction
Reference
The following documents are referenced. * FlexRay Communications System Protocol Specification, Version 2.1 * FlexRay Communications System Electrical Physical Layer Specification, Version 2.1
3.1.2
Glossary
Table 3-1. List of Terms (Sheet 1 of 2)
Term Definition Buffer Control Unit. Handles message buffer access. Communication Controller Clock Domain Crosser Controller Host Interface The actual length of a cycle in T for the ideal controller (+/- 0 ppm) External Bus Interface FlexRay Memory. Memory to store message buffer payload, header, and status, and to store synchronization frame related tables. Frame Start Sequence Host Interface. Provides host access to FlexRay module. The FlexRay CC host MCU Look Up Table. Stores message buffer header index value. Message Buffer Message Buffer Index: the position of a header field entry within the header area. If the header area is accessed as an array, this is the same as the array index of the entry. Message Buffer Number: Position of message buffer configuration registers within the register map. For example, Message Buffer Number 5 corresponds to the MBCCS5 register. Microcontroller Unit Microtick Macrotick Media Access Test Symbol
This section provides a list of terms used in the description of the FlexRay module.
BCU CC CDC CHI Cycle length in T EBI FRM FSS HIF Host LUT MB MBIDX MBNum MCU T MT MTS
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 57
FlexRay Module (FLEXRAYV2)
Table 3-1. List of Terms (Sheet 2 of 2)
Term NIT PE POC Rx SEQ TCU Tx Network Idle Time Protocol Engine Protocol Operation Control. Each state of the POC is denoted by POC:state Reception Sequencer Engine Time Control Unit Transmission Definition
3.1.3
Color Coding
Throughout this chapter types of items are highlighted through the use of an italicized color font. FlexRay protocol parameters, constants and variables are highlighted with blue italics. An example is the parameter gdActionPointOffset. FlexRay protocol states are highlighted in green italics. An example is the state POC:normal active.
3.1.4
Overview
The FlexRay module is a FlexRay communication controller that implements the FlexRay Communications System Protocol Specification, Version 2.1. The FlexRay module has three main components: * Controller host interface (CHI) * Protocol engine (PE) * Clock domain crossing unit (CDC) A block diagram of the FlexRay module with its surrounding modules is given in Figure 3-1.
MFR4300 Data Sheet, Rev. 3 58 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
FlexRay Module EBI CHI HIF config Clock Domain Crossing PE SEQ
RXD_BG1 TXD_BG1 TXEN1# RXD_BG2 TXD_BG2 TXEN2#
SEARCH
TxA
LUT FlexRay Memory
BCU
RxA
DBG0
MIF
TCU
DBG1 DBG2 DBG3
Figure 3-1. FlexRay Module Block Diagram
The protocol engine has two transmitter units TxA and TxB and two receiver units RxA and RxB for sending and receiving frames through the two FlexRay channels. The time control unit (TCU) is responsible for maintaining global clock synchronization to the FlexRay network. The overall activity of the PE is controlled by the sequencer engine (SEQ). The controller host interface provides host access to the module's configuration, control, and status registers, as well as to the message buffer configuration, control, and status registers. The message buffers themselves, which contain the frame header and payload data received or to be transmitted, and the slot status information, are stored in the FlexRay Memory (FRM). The clock domain crossing unit implements signal crossing from the CHI clock domain to the PE clock domain and vice versa, to allow for asynchronous PE and CHI clock domains. The FlexRay module stores the frame header and payload data of frames received or of frames to be transmitted in the FRM. The application accesses the FRM to retrieve and provide the frames to be processed by the FlexRay module. In addition to the frame header and payload data, the FlexRay module stores the synchronization frame related tables in the FRM for application processing. NOTE The FlexRay module does not provide a memory protection scheme for the FlexRay Memory.
3.1.5
Features
The FlexRay module provides the following features:
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 59
FlexRay Module (FLEXRAYV2)
* * *
*
*
* *
* * *
*
*
* * *
FlexRay Communications System Protocol Specification, Version 2.1 compliant protocol implementation FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 compliant bus driver interface single channel support -- internal channel A and FlexRay Port A can be configured to be connected either to physical FlexRay channel A or physical FlexRay channel B. 128 configurable message buffers with -- individual frame ID filtering -- individual channel ID filtering -- individual cycle counter filtering message buffer header, status and payload data stored in dedicated FlexRay Memory -- allows for flexible and efficient message buffer implementation -- consistent data access ensured by means of buffer locking scheme -- application can lock multiple buffers at the same time size of message buffer payload data section configurable from 0 up to 254 bytes two independent message buffer segments with configurable size of payload data section -- each segment can contain message buffers assigned to the static segment and message buffers assigned to the dynamic segment at the same time zero padding for transmit message buffers in static segment -- applied when the frame payload length exceeds the size of the message buffer data section transmit message buffers configurable with state/event semantics message buffers can be configured as -- receive message buffer -- single buffered transmit message buffer -- double buffered transmit message buffer (combines two single buffered message buffer) individual message buffer reconfiguration supported -- means provided to safely disable individual message buffers -- disabled message buffers can be reconfigured two independent receive FIFOs -- one receive FIFO per channel -- up to 255 entries for each FIFO -- global frame ID filtering, based on both value/mask filters and range filters -- global channel ID filtering -- global message ID filtering for the dynamic segment 4 configurable slot error counters 4 dedicated slot status indicators -- used to observe slots without using receive message buffers measured value indicators for the clock synchronization
MFR4300 Data Sheet, Rev. 3
60
Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
* * * *
-- internal synchronization frame ID and synchronization frame measurement tables can be copied into the FlexRay Memory fractional macroticks are supported for clock correction maskable interrupt sources provided via individual and combined interrupt lines 1 absolute timer 1 timer that can be configured to absolute or relative
3.1.6
3.1.6.1
Modes of Operation
Disabled Mode
This is the default mode the FlexRay module enters during hard reset. The FlexRay module indicates that it is in the Disabled Mode by negating the FlexRay module enable bit MEN in the Module Configuration Register (MCR). The protocol engine is in its reset state. No communication is performed on the FlexRay bus. All registers with the write access conditions Any Time and Disabled Mode can be accessed for writing as stated in Section 3.3.2, "Register Descriptions". The application can configure the FlexRay module by accessing the FlexRay module configuration bits and fields in the Module Configuration Register (MCR). The FlexRay module leaves disabled mode when the application sets the FlexRay module enable bit MEN in the Module Configuration Register (MCR) The FlexRay module then deasserts the protocol engine reset and puts the protocol engine into the POC:default config state. NOTE After the application has enabled the FlexRay module it cannot disable the FlexRay module later on.
3.1.6.2
Normal Mode
In this mode the FlexRay module is fully functional. The FlexRay module indicates that it is in normal mode by asserting the FlexRay module enable bit (MEN) in the Module Configuration Register (MCR). This mode is entered when the application requests the FlexRay module to leave the disabled mode. If this mode is entered, the protocol engine is in its POC:default config state. Depending on the values of the SCM, CHA, and CHB bits in the Module Configuration Register (MCR), the corresponding FlexRay bus driver ports are enabled and driven. The application can transition the protocol engine into other protocol states using the Protocol Operation Control Register (POCR). For details regarding protocol states, see FlexRay Communications System Protocol Specification, Version 2.1.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 61
FlexRay Module (FLEXRAYV2)
3.2
External Signal Description
This section lists and describes the FlexRay module signals, connected to external pins. These signals are summarized in Table 3-2 and described in detail in Section 3.2.1, "Detailed Signal Descriptions". NOTE The off chip signals RXD_BG1, TXD_BG1, and TXEN1# are available on each package option. The availability of the other off chip signals depends on the package option.
Table 3-2. External Signal Properties
Name RXD_BG1 TXD_BG1 TXEN1# RXD_BG2 TXD_BG2 TXEN2# DBG0 DBG1 DBG2 DBG3 Direction Input Output Output Input Output Output Output Output Output Output Active -- -- Low -- -- Low -- -- -- -- Reset -- 1 1 -- 1 1 0 0 0 0 Function Receive Data Channel A Transmit Data Channel A Transmit Enable Channel A Receive Data Channel B Transmit Data Channel B Transmit Enable Channel B Debug Strobe Signal 0 Debug Strobe Signal 1 Debug Strobe Signal 2 Debug Strobe Signal 3
3.2.1
Detailed Signal Descriptions
This section provides a detailed description of the FlexRay module signals, connected to external pins.
3.2.1.1
RXD_BG1 -- Receive Data Channel A
The RXD_BG1 signal carries the receive data for channel A from the corresponding FlexRay bus driver.
3.2.1.2
TXD_BG1 -- Transmit Data Channel A
The TXD_BG1 signal carries the transmit data for channel A to the corresponding FlexRay bus driver.
3.2.1.3
TXEN1# -- Transmit Enable Channel A
The TXEN1# signal indicates to the FlexRay bus driver that the FlexRay module is attempting to transmit data on channel A.
3.2.1.4
RXD_BG2 -- Receive Data Channel B
The RXD_BG2 signal carries the receive data for channel B from the corresponding FlexRay bus driver.
MFR4300 Data Sheet, Rev. 3 62 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.2.1.5
TXD_BG2 -- Transmit Data Channel B
The TXD_BG2 signal carries the transmit data for channel B to the corresponding FlexRay bus driver
3.2.1.6
TXEN2# -- Transmit Enable Channel B
The TXEN2# signal indicates to the FlexRay bus driver that the FlexRay module is attempting to transmit data on channel B.
3.2.1.7
DBG3, DBG2, DBG1, DBG0 -- Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe signal selection refer to Section 3.4.16, "Strobe Signal Support".
3.3
Memory Map and Register Description
The FlexRay module occupies 1280 bytes of address space starting at address 0x0000.
3.3.1
Memory Map
Table 3-3. FlexRay Memory Map (Sheet 1 of 4)
The complete memory map of the FlexRay module is shown in Table 3-3.
Address
Register Module Configuration and Control
Access
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E
Module Version Register (MVR) Module Configuration Register (MCR) Reserved Reserved Strobe Signal Control Register (STBSCR) Strobe Port Control Register (STBPCR) Message Buffer Data Size Register (MBDSR) Message Buffer Segment Size and Utilization Register (MBSSUTR) Test Registers
R R/W R R R/W R/W R/W R/W
0x0010 0x0012
Reserved Reserved Interrupt and Error Handling
R R
0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022
Protocol Operation Control Register (POCR) Global Interrupt Flag and Enable Register (GIFER) Protocol Interrupt Flag Register 0 (PIFR0) Protocol Interrupt Flag Register 1 (PIFR1) Protocol Interrupt Enable Register 0 (PIER0) Protocol Interrupt Enable Register 1 (PIER1) CHI Error Flag Register (CHIERFR) Message Buffer Interrupt Vector Register (MBIVEC)
R/W R/W R/W R/W R/W R/W R/W R
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 63
FlexRay Module (FLEXRAYV2)
Table 3-3. FlexRay Memory Map (Sheet 2 of 4)
Address 0x0024 0x0026 Register Channel A Status Error Counter Register (CASERCR) Channel B Status Error Counter Register (CBSERCR) Protocol Status 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C 0x003E Protocol Status Register 0 (PSR0) Protocol Status Register 1 (PSR1) Protocol Status Register 2 (PSR2) Protocol Status Register 3 (PSR3) Macrotick Counter Register (MTCTR) Cycle Counter Register (CYCTR) Slot Counter Channel A Register (SLTCTAR) Slot Counter Channel B Register (SLTCTBR) Rate Correction Value Register (RTCORVR) Offset Correction Value Register (OFCORVR) Combined Interrupt Flag Register (CIFRR) Reserved Sync Frame Counter and Tables 0x0040 0x0042 0x0044 Sync Frame Counter Register (SFCNTR) Sync Frame Table Offset Register (SFTOR) Sync Frame Table Configuration, Control, Status Register (SFTCCSR) Sync Frame Filter 0x0046 0x0048 0x004A Sync Frame ID Rejection Filter Register (SFIDRFR) Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR) Network Management Vector 0x004C 0x004E 0x0050 0x0052 0x0054 0x0056 0x0058 Network Management Vector Register 0 (NMVR0) Network Management Vector Register 1 (NMVR1) Network Management Vector Register 2 (NMVR2) Network Management Vector Register 3 (NMVR3) Network Management Vector Register 4 (NMVR4) Network Management Vector Register 5 (NMVR5) Network Management Vector Length Register (NMVLR) Timer Configuration 0x005A 0x005C 0x005E 0x0060 0x0062 Timer Configuration and Control Register (TICCR) Timer 1 Cycle Set Register (TI1CYSR) Timer 1 Macrotick Offset Register (TI1MTOR) Timer 2 Configuration Register 0 (TI2CR0) Timer 2 Configuration Register 1 (TI2CR1) Slot Status Configuration 0x0064 0x0066 Slot Status Selection Register (SSSR) Slot Status Counter Condition Register (SSCCR) R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W R/W R/W R R/W R/W R R R R/W R R R R R R R R Access R R
MFR4300 Data Sheet, Rev. 3 64 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-3. FlexRay Memory Map (Sheet 3 of 4)
Address Register Slot Status 0x0068 0x006A 0x006C 0x006E 0x0070 0x0072 0x0074 0x0076 0x0078 0x007A 0x007C 0x007E Slot Status Register 0 (SSR0) Slot Status Register 1 (SSR1) Slot Status Register 2 (SSR2) Slot Status Register 3 (SSR3) Slot Status Register 4 (SSR4) Slot Status Register 5 (SSR5) Slot Status Register 6 (SSR6) Slot Status Register 7 (SSR7) Slot Status Counter Register 0 (SSCR0) Slot Status Counter Register 1 (SSCR1) Slot Status Counter Register 2 (SSCR2) Slot Status Counter Register 3 (SSCR3) MTS Generation 0x0080 0x0082 MTS A Configuration Register (MTSACFR) MTS B Configuration Register (MTSBCFR) Shadow Buffer Configuration 0x0084 Receive Shadow Buffer Index Register (RSBIR) Receive FIFO -- Configuration 0x0086 0x0088 0x008A Receive FIFO Selection Register (RFSR) Receive FIFO Start Index Register (RFSIR) Receive FIFO Depth and Size Register (RFDSR) Receive FIFO - Status 0x008C 0x008E Receive FIFO A Read Index Register (RFARIR) Receive FIFO B Read Index Register (RFBRIR) Receive FIFO - Filter 0x0090 0x0092 0x0094 0x0096 0x0098 0x009A Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) Receive FIFO Range Filter Configuration Register (RFRFCFR) Receive FIFO Range Filter Control Register (RFRFCTR) Dynamic Segment Status 0x009C 0x009E Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) Protocol Configuration 0x00A0 ... 0x00DC Protocol Configuration Register 0 (PCR0) ... Protocol Configuration Register 30 (PCR30) R/W - R/W R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R Access
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 65
FlexRay Module (FLEXRAYV2)
Table 3-3. FlexRay Memory Map (Sheet 4 of 4)
Address 0x00DE ... 0x00FE Register Reserved Message Buffers Configuration, Control, Status 0x0100 0x0102 0x0104 0x0106 ... 0x04F8 0x04FA 0x04FC 0x04FE Message Buffer Configuration, Control, Status Register 0 (MBCCSR0) Message Buffer Cycle Counter Filter Register 0 (MBCCFR0) Message Buffer Frame ID Register 0 (MBFIDR0) Message Buffer Index Register 0 (MBIDXR0) ... Message Buffer Configuration, Control, Status Register 127 (MBCCSR127) Message Buffer Cycle Counter Filter Register 127 (MBCCFR127) Message Buffer Frame ID Register 127 (MBFIDR127) Message Buffer Index Register 127 (MBIDXR127) R/W R/W R/W R/W ... R/W R/W R/W R/W Access R
3.3.2
Register Descriptions
This section provides detailed descriptions of all registers in ascending address order, presented as 16-bit wide entities. Table 3-4 provides a key for the register figures and register tables.
Table 3-4. Register Access Conventions
Convention Description The shaded field indicates that the bit or field is not writeable. R* The R* item indicates a reserved bit or field. The FlexRay module will not change its value. The application must not write any value different from the reset value to this bit or field.
Reset Value 0 1 - Resets to zero. Resets to one. Not defined after and not affected by reset.
3.3.2.1
Register Reset
All registers except the Message Buffer Cycle Counter Filter Registers (MBCCFRn), Message Buffer Frame ID Registers (MBFIDRn), and Message Buffer Index Registers (MBIDXRn) are reset to their reset value on system reset. The registers mentioned above are located in physical memory blocks and, thus, they are not affected by reset. For some register fields, additional reset conditions exist. These additional reset conditions are mentioned in the detailed description of the register. The additional reset conditions are explained in Table 3-5.
MFR4300 Data Sheet, Rev. 3 66 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-5. Additional Register Reset Conditions
Condition Protocol RUN Command Message Buffer Disable Description The register field is reset when the application writes to RUN command "0101" to the POCCMD field in the Protocol Operation Control Register (POCR). The register field is reset when the application has disabled the message buffer. This happens when the application writes `1' to the message buffer disable trigger bit MBCCSRn.EDT while the message buffer is enabled (MBCCSn.EDS = 1) and the FlexRay module grants the disable to the application by clearing the MBCCSRn.EDS bit.
3.3.2.2
Register Write Access
This section describes the write access restriction terms that apply to all registers. 3.3.2.2.1 Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register description. A description of the write access conditions is given in Table 3-6. If, for a specific register bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or field is ignored without any notification. The values of the bits or fields are not changed. The condition term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
Table 3-6. Register Write Access Restrictions
Condition Any Time Disabled Mode Normal Mode POC:config MB_DIS MB_LCK Indication MCR.MEN = `0' MCR.MEN = `1' PSR0.PROTSTATE = POC:config MBCCSRn.EDS = `0' MBCCSRn.LCKS = `1' No write access restriction. Write access only when the FlexRay module is in Disabled Mode. Write access only when the FlexRay module is in Normal Mode. Write access only when the Protocol is in the POC:config state. Write access only when the related Message Buffer is disabled. Write access only when the related Message Buffer is locked. Description
3.3.2.2.2
Register Write Access Requirements
For some of the registers, a 16-bit wide write access is required to ensure correct operation. This write access requirement is stated in the detailed register description for each register affected 3.3.2.2.3 Internal Register Access
The following memory mapped registers are used to access multiple internal registers. * Strobe Signal Control Register (STBSCR) * Slot Status Selection Register (SSSR) * Slot Status Counter Condition Register (SSCCR) * Receive Shadow Buffer Index Register (RSBIR) Each of these memory mapped registers provides a SEL field and a WMD bit. The SEL field is used to select the internal register. The WMD bit controls the write mode. If the WMD bit is set to `0' during the write access, all fields of the internal register are updated. If the WMD bit set to `1', only the SEL field is
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 67
FlexRay Module (FLEXRAYV2)
changed. All other fields of the internal register remain unchanged. This allows for reading back the values of the selected internal register in a subsequent read access.
3.3.2.3
0x0000
15
Module Version Register (MVR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 1
CHIVER 1 0 1 0 1 0 0 1
PEVER 1 0 1 0 1
Figure 3-2. Module Version Register (MVR)
This register provides the FlexRay module version number. The module version number is derived from the CHI version number and the PE version number.
Table 3-7. MVR Field Descriptions
Field 15-8 CHIVER 7-0 PEVER Description CHI Version Number -- This field provides the version number of the controller host interface. PE Version Number -- This field provides the version number of the protocol engine.
3.3.2.4
0x0002
15
Module Configuration Register (MCR)
Write: MEN, SCM, CHB, CHA: Disabled Mode SFFE: Disabled Mode or POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
MEN 0
0 0
SCM 0
CHB 0
CHA SFFE 0 0
0 0
R* 0
0 0
0 0
0 0
R* 0 0
R* 0 0
0 0
Figure 3-3. Module Configuration Register (MCR)
This register defines the global configuration of the FlexRay module.
MFR4300 Data Sheet, Rev. 3 68 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-8. MCR Field Descriptions
Field 15 MEN Description Module Enable -- This bit indicates whether or not the FlexRay module is in the Disabled Mode. The application requests the FlexRay module to leave the Disabled Mode by writing 1 to this bit. Before leaving the Disabled Mode, the application must configure the SCM, CHB, CHA, TMODE values. For details see Section 3.1.6, "Modes of Operation". 0 Write: ignored, FlexRay module disable not possible Read: FlexRay module disabled 1 Write: enable FlexRay module Read: FlexRay module enabled Note: If the FlexRay module is enabled it can not be disabled. Single Channel Device Mode -- This control bit defines the channel device mode of the FlexRay module as described in Section 3.4.10, "Channel Device Modes". 0 FlexRay module works in dual channel device mode 1 FlexRay module works in single channel device mode Channel Enable -- protocol related parameter: pChannels The semantic of these control bits depends on the channel device mode controlled by the SCM bit and is given Table 3-9. Synchronization Frame Filter Enable -- This bit controls the filtering for received synchronization frames. For details see Section 3.4.15, "Sync Frame Filtering". 0 Synchronization frame filtering disabled 1 Synchronization frame filtering enabled Reserved -- This bit is reserved. It is read as `0'. Application must not write `1' to this bit. Reserved -- This bit is reserved. It is read as `0'. Application must not write `1' to this bit. Reserved -- This field is reserved. It is read as `000'. Application must not write `1' to any bit.
13 SCM
12-11 CHB CHA 10 SFFE
8 R* 4 R* 3-1 R*
Table 3-9. Channel Enable Mapping (Sheet 1 of 2)
SCM CHB CHA Description Dual Channel Device Modes ports RXD_BG1, TXD_BG1, and TXEN1# not driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# not driven by FlexRay module PE channel 0 idle PE channel 1 idle ports RXD_BG1, TXD_BG1, and TXEN1# driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# not driven by FlexRay module PE channel 0 active PE channel 1 idle ports RXD_BG1, TXD_BG1, and TXEN1# not driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# driven by FlexRay module PE channel 0 idle PE channel 1 active ports RXD_BG1, TXD_BG1, and TXEN1# driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# driven by FlexRay module PE channel 0 active PE channel 1 active Single Channel Device Mode
0
0
0 0 1
1
0
1
1
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 69
FlexRay Module (FLEXRAYV2)
Table 3-9. Channel Enable Mapping (Sheet 2 of 2)
SCM CHB CHA Description ports RXD_BG1, TXD_BG1, and TXEN1# not driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# not driven by FlexRay module PE channel 0 idle PE channel 1 idle ports RXD_BG1, TXD_BG1, and TXEN1# driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# not driven by FlexRay module PE channel 0 active PE channel 1 idle ports RXD_BG1, TXD_BG1, and TXEN1# driven by FlexRay module ports RXD_BG2, TXD_BG2, and TXEN1# not driven by FlexRay module PE channel 0 active, uses cCrcInit[B] (see Figure 3-132) PE channel 1 idle reserved
0
0
1
0
1
1 1
0 1
3.3.2.5
0x0008
15
Strobe Signal Control Register (STBSCR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5 4 3 2
Write: Any Time
1 0
R Reset
0 0 0 0 0
W WMD
SEL 0 0 0 0
0 0
0 0
0 0
ENB 0
0 0
0 0
STBPSEL 0 0
Figure 3-4. Strobe Signal Control Register (STBSCR)
This register is used to assign the individual protocol timing related strobe signals given in Table 3-11 to the external strobe ports. Each strobe signal can be assigned to at most one strobe port. Each write access to registers overwrites the previously written ENB and STBPSEL values for the signal indicated by SEL. If more than one strobe signal is assigned to one strobe port, the current values of the strobe signals are combined with a binary OR and presented at the strobe port. If no strobe signal is assigned to a strobe port, the strobe port carries logic 0. For more detailed and timing information refer to Section 3.4.16, "Strobe Signal Support". NOTE In single channel device mode, channel B related strobe signals are undefined and should not be assigned to the strobe ports.
Table 3-10. STBSCR Field Descriptions (Sheet 1 of 2)
Field 15 WMD 14-8 SEL Description Write Mode -- This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. Strobe Signal Select -- This control field selects one of the strobe signals given in Table 3-11 to be enabled or disabled and assigned to one of the four strobe ports given in Table 3-11.
MFR4300 Data Sheet, Rev. 3 70 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-10. STBSCR Field Descriptions (Sheet 2 of 2)
Field 4 ENB Description Strobe Signal Enable -- The control bit is used to enable and to disable the strobe signal selected by STBSSEL. 0 Strobe signal is disabled and not assigned to any strobe port. 1 Strobe signal is enabled and assigned to the strobe port selected by STBPSEL. Strobe Port Select -- This field selects the strobe port that the strobe signal selected by the SEL is assigned to. All strobe signals that are enabled and assigned to the same strobe port are combined with a binary OR operation. 00 assign selected signal to DBG0 01 assign selected signal to DBG1 10 assign selected signal to DBG2 11 assign selected signal to DBG3
1-0 STBPSEL
.;
Table 3-11. Strobe Signal Mapping (Sheet 1 of 3)
SEL Description dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 hex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A poc_startup_state[0] (for coding see PSR0[4]) poc_startup_state[1] (for coding see PSR0[5]) poc_startup_state[2] (for coding see PSR0[6]) poc_startup_state[3] (for coding see PSR0[7]) poc_state[0] (for coding see PSR0[8]) poc_state[1] (for coding see PSR0[9]) poc_state[2] (for coding see PSR0[10]) channel idle indicator receive data after glitch filtering synchronization edge strobe header received wakeup symbol decoded MTS or CAS symbol decoded frame decoded channel idle detected start of communication element detected potential frame start channel A B A B A B A B A B A B A B A B A B A B level value pulse pulse pulse pulse pulse pulse pulse pulse +5 +4 +4 +4 +5 +4 +4 +4 +4 +4 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 value 0 MT start Channel Type Offset1 Reference
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 71
FlexRay Module (FLEXRAYV2)
Table 3-11. Strobe Signal Mapping (Sheet 2 of 3)
SEL Description dec 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 hex 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 wakeup collision detected content error detected syntax error detected start transmission of wakeup pattern start transmission of MTS or CAS symbol start of transmission end of transmission static segment indicator dynamic segment indicator symbol window indicator NIT indicator action point sync calculation complete2 start of offset correction cycle count[0] cycle count[1] cycle count[2] cycle count[3] cycle count[4] cycle count[5] slot count[0] slot count[1] slot count[2] slot count[3] slot count[4] slot count[5] slot count[6] slot count[7] slot count[8] slot count[9] slot count[10] A value 0 MT start value -2 MT start A B A B A B A B A B A B A B pulse level pulse pulse pulse pulse pulse level level level level pulse pulse pulse +5 +4 +4 -1 -1 -1 -1 0 0 0 0 -1 -2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 RXD_BG1 RXD_BG2 TXD_BG1 TXD_BG2 TXD_BG1 TXD_BG2 TXD_BG1 TXD_BG2 TXD_BG1 TXD_BG2 MT start MT start MT start MT start TXD_BG1 MT start Channel Type Offset1 Reference
MFR4300 Data Sheet, Rev. 3 72 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-11. Strobe Signal Mapping (Sheet 3 of 3)
SEL Description dec 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
1
Channel
Type
Offset1
Reference
hex 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 slot count[0] slot count[1] slot count[2] slot count[3] slot count[4] slot count[5] slot count[6] slot count[7] slot count[8] slot count[9] slot count[10] cycle start slot start minislot start arm mt A B pulse pulse pulse value value 0 0 0 +1 +1 MT start MT start MT start MT start MT start B value 0 MT start
Given in PE clock cycles 2 Indicates internal PE event not directly related to FlexRay bus timing
3.3.2.6
0x000A
15
Strobe Port Control Register (STBPCR)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STB3EN
STB2EN
STB1EN 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-5. Strobe Port Control Register (STBPCR)
This register is used to enable and disable the strobe port signals. Each disabled port will stay disabled even when strobe signals are assigned to it.
Table 3-12. STBPCR Field Descriptions
Field 3 STB3EN 2 STB2EN Description Strobe Port 3 Enable -- This control bit defines whether the DBG3 port is enabled or disabled. 0 Strobe port DBG3 disabled 1 Strobe port DBG3 enabled Strobe Port 2 Enable -- This control bit defines whether the DBG2 port is enabled or disabled. 0 Strobe port DBG2 disabled 1 Strobe port DBG2 enabled
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 73
STB0EN 0
FlexRay Module (FLEXRAYV2)
Table 3-12. STBPCR Field Descriptions (Continued)
Field 1 STB1EN 0 STB0EN Description Strobe Port 1 Enable -- This control bit defines whether the DBG1 port is enabled or disabled. 0 Strobe port DBG1 disabled 1 Strobe port DBG1 enabled Strobe Port 0 Enable -- This control bit defines whether the DBG0 port is enabled or disabled. 0 Strobe port DBG0 disabled 1 Strobe port DBG0 enabled
3.3.2.7
0x000C
15
Message Buffer Data Size Register (MBDSR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0 0 0 0
MBSEG2DS 0 0 0 0
0 0 0 0 0
MBSEG1DS 0 0 0 0
Figure 3-6. Message Buffer Data Size Register (MBDSR)
This register defines the size of the message buffer data section for the two message buffer segments in a number of two-byte entities. The FlexRay module provides two independent segments for the individual message buffers. All individual message buffers within one segment have to have the same size for the message buffer data section. This size can be different for the two message buffer segments.
Table 3-13. MBDSR Field Descriptions
Field Description
14-8 Message Buffer Segment 2 Data Size -- The field defines the size of the message buffer data section in MBSEG2DS two-byte entities for message buffers within the second message buffer segment. 6-0 Message Buffer Segment 1 Data Size -- The field defines the size of the message buffer data section in MBSEG1DS two-byte entities for message buffers within the first message buffer segment.
3.3.2.8
0x000E
15
Message Buffer Segment Size and Utilization Register (MBSSUTR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0 1 1
LAST_MB_SEG1 1 1 1 1 1
0 0 1 1
LAST_MB_UTIL 1 1 1 1 1
Figure 3-7. Message Buffer Segment Size and Utilization Register (MBSSUTR)
This register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer.
MFR4300 Data Sheet, Rev. 3 74 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-14. MBSSUTR Field Descriptions
Field Description
14-8 Last Message Buffer In Segment 1 -- This field defines the message buffer number of the last individual LAST_MB_SEG1 message buffer that is assigned to the first message buffer segment. The individual message buffers in the first segment correspond to the message buffer control registers MBCCSRn, MBCCFRn, MBFIDRn, MBIDXRn with n <= LAST_MB_SEG1. The first message buffer segment contains LAST_MB_SEG1+1 individual message buffers. Note: The first message buffer segment contains at least one individual message buffer. The individual message buffers in the second message buffer segment correspond to the message buffer control registers MBCCSRn, MBCCFRn, MBFIDRn, MBIDXRn with LAST_MB_SEG1 < n < 128. Note: If LAST_MB_SEG1 = 127 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. 6-0 LAST_MB_UTIL Last Message Buffer Utilized -- This field defines the message buffer number of last utilized individual message buffer. The message buffer search engine examines all individual message buffer with a message buffer number n <= LAST_MB_UTIL. Note: If LAST_MB_UTIL=LAST_MB_SEG1 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty.
3.3.2.9
0x0014
15
Protocol Operation Control Register (POCR)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reset
0 0
0 0
0 0
0 0 0
0 EOC_AP 0 0
0 ERC_AP 0
BSY WMC 0
0 0
0 0
0 0 0
W WME
POCCMD 0 0 0
Figure 3-8. Protocol Operation Control Register (POCR)
The application uses this register to issue * protocol control commands * external clock correction commands Protocol control commands are issued by writing to the POCCMD field. For more information on protocol control commands, see Section 3.6.2, "Protocol Control Command Execution". External clock correction commands are issued by writing to the EOC_AP and ERC_AP fields. For more information on external clock correction, refer to Section 3.4.11, "External Clock Synchronization".
Table 3-15. POCR Field Descriptions (Sheet 1 of 2)
Field 15 WME 11-10 EOC_AP Description Write Mode External Correction -- This bit controls the write mode of the EOC_AP and ERC_AP fields. 0 Write to EOC_AP and ERC_AP fields on register write. 1 No write to EOC_AP and ERC_AP fields on register write. External Offset Correction Application -- This field is used to trigger the application of the external offset correction value defined in the Protocol Configuration Register 29 (PCR29). 00 do not apply external offset correction value 01 reserved 10 subtract external offset correction value 11 add external offset correction value
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 75
FlexRay Module (FLEXRAYV2)
Table 3-15. POCR Field Descriptions (Sheet 2 of 2)
Field 9-8 ERC_AP Description External Rate Correction Application -- This field is used to trigger application of the external rate correction value defined in the Protocol Configuration Register 21 (PCR21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value Protocol Control Command Write Busy -- This status bit indicates the acceptance of the protocol control command issued by the application via the POCCMD field. The FlexRay module sets this status bit when the application has issued a protocol control command via the POCCMD field. The FlexRay module clears this status bit when protocol control command was accepted by the PE.When the application issues a protocol control command while the BSY bit is asserted, the FlexRay module ignores this command, sets the protocol command ignored error flag PCMI_EF in the CHI Error Flag Register (CHIERFR), and will not change the value of the POCCMD field. 0 Command write idle, command accepted and ready to receive new protocol command. 1 Command write busy, command not yet accepted, not ready to receive new protocol command. Write Mode Command -- This bit controls the write mode of the POCCMD field. 0 Write to POCCMD field on register write. 1 Do not write to POCCMD field on register write. Protocol Control Command -- The application writes to this field to issue a protocol control command to the PE. The FlexRay module sends the protocol command to the PE immediately. While the transfer is running, the BSY bit is set. 0000 ALLOW_COLDSTART -- Immediately activate capability of node to cold start cluster. 0001 ALL_SLOTS -- Delayed1 transition to the all slots transmission mode. 0010 CONFIG -- Immediately transition to the POC:config state. 0011 FREEZE -- Immediately transition to the POC:halt state. 0100 READY, CONFIG_COMPLETE -- Immediately transition to the POC:ready state. 0101 RUN -- Immediately transition to the POC:startup start state. 0110 DEFAULT_CONFIG -- Immediately transition to the POC:default config state. 0111 HALT -- Delayed transition to the POC:halt state 1000 WAKEUP -- Immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 RESET2 -- Immediately reset the Protocol Engine. 1101 reserved 1110 reserved 1111 reserved
7 BSY
WMC
3-0 POCCMD
1 2
Delayed means on completion of current communication cycle. Additional to FlexRay Communications System Protocol Specification, Version 2.1
NOTE After sending the RESET command, it is mandatory to execute the command sequence described in Section 3.6.3, "Protocol Reset Command" immediately, to reach the DEFAULT CONFIG state correctly.
MFR4300 Data Sheet, Rev. 3 76 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.10
0x0016
15
Global Interrupt Flag and Enable Register (GIFER)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNEBIE
W Reset 0 0 0
MIE 0 0 0
PRIE CHIE 0 0
WUPIE
WUPIF
R
MIF
PRIF
CHIF
RBIF
TBIF
FNEAIE
FNEBIF
FNEAIF
RBIE 0
TBIE 0
0
0
0
0
0
0
Figure 3-9. Global Interrupt Flag and Enable Register (GIFER)
This register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these flags is depicted in Figure 3-141. For more details on interrupt generation, see Section 3.4.19, "Interrupt Support. These flags are cleared automatically when all of the corresponding interrupt flags or interrupt enables in the related interrupt flag and enable registers are cleared by the application. In this register the application can clear only the interrupt flags WUPIF, FNEBIF, and FNEAIF, by writing `1' to each them. Writing `0' will not change the flag state. If the application clears a flag and the FlexRay module sets the flag on the same cycle, then that flag remains set.
Table 3-16. GIFER Field Descriptions (Sheet 1 of 3)
Field 15 MIF Description Module Interrupt Flag -- This flag is set if at least one of the other interrupt flags is in this register is asserted and the related interrupt enable is asserted, too. The FlexRay module generates the module interrupt request if MIE is asserted. 0 No interrupt flag is asserted or no interrupt enable is set 1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too Protocol Interrupt Flag -- This flag is set if at least one of the individual protocol interrupt flags in the Protocol Interrupt Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1) is asserted and the related interrupt enable flag is asserted, too. The FlexRay module generates the combined protocol interrupt request if the PRIE flag is asserted. 0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set. 1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1. CHI Interrupt Flag -- This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register (CHIERFR) is asserted and the chi error interrupt enable GIFER.CHIE is asserted. The FlexRay module generates the combined CHI error interrupt if the CHIE flag is asserted, too. 0 All CHI error flags are equal to 0 or the chi error interrupt is disabled 1 At least one CHI error flag is asserted and chi error interrupt is enabled Wakeup Interrupt Flag -- This flag is set when the FlexRay module has received a wakeup symbol on the FlexRay bus. The application can determine on which channel the wakeup symbol was received by reading the related wakeup flags WUB and WUA in the Protocol Status Register 3 (PSR3). The FlexRay module generates the wakeup interrupt request if the WUPIE flag is asserted. 0 No wakeup condition or interrupt disabled 1 Wakeup symbol received on FlexRay bus and interrupt enabled Receive FIFO channel B Not Empty Interrupt Flag -- This flag is set when the receive FIFO for channel B is not empty. If the application writes 1 to this bit, the FlexRay module updates the FIFO status, increments or wraps the FIFO read index in the Receive FIFO B Read Index Register (RFBRIR) and clears the interrupt flag if the FIFO B is now empty. If the FIFO is still not empty, the FlexRay module sets this flag again. The FlexRay module generates the Receive FIFO B Not empty interrupt if the FNEBIE flag is asserted. 0 Receive FIFO B is empty or interrupt is disabled 1 Receive FIFO B is not empty and interrupt enabled MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 77
13 PRIF
13 CHIF
12 WUPIF
11 FNEBIF
FlexRay Module (FLEXRAYV2)
Table 3-16. GIFER Field Descriptions (Sheet 2 of 3)
Field 10 FNEAIF Description Receive FIFO channel A Not Empty Interrupt Flag -- This flag is set when the receive FIFO for channel A is not empty. If the application writes 1 to this bit, the FlexRay module updates the FIFO status, increments or wraps the FIFO read index in the Receive FIFO A Read Index Register (RFARIR) and clears the interrupt flag if the FIFO A is now empty. If the FIFO is still not empty, the FlexRay module sets this flag again. The FlexRay module generates the Receive FIFO A Not empty interrupt if the FNEAIE flag is asserted. 0 Receive FIFO A is empty or interrupt is disabled 1 Receive FIFO A is not empty and interrupt enabled Receive Message Buffer Interrupt Flag -- This flag is set if for at least one of the individual receive message buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are asserted. The application can not clear this RBIF flag directly. This flag is cleared by the FlexRay module when all of the interrupt flags MBIF of the individual receive message buffers are cleared by the application or if the application has cleared the interrupt enables bit MBIE. 0 None of the individual receive message buffers has the MBIF and MBIE flag asserted. 1 At least one individual receive message buffer has the MBIF and MBIE flag asserted. Transmit Buffer Interrupt Flag -- This flag is set if for at least one of the individual single or double transmit message buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are equal to `1'. The application can not clear this TBIF flag directly. This flag is cleared by the FlexRay module when either all of the individual interrupt flags MBIF of the individual transmit message buffers are cleared by the application or the host has cleared the interrupt enables bit MBIE. 0 None of the individual transmit message buffers has the MBIF and MBIE flag asserted. 1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted. Module Interrupt Enable -- This flag controls if the module interrupt line is asserted when the MIF flag is set. 0 Disable interrupt line 1 Enable interrupt line Protocol Interrupt Enable -- This flag controls if the protocol interrupt line is asserted when the PRIF flag is set. 0 Disable interrupt line 1 Enable interrupt line CHI Interrupt Enable -- This flag controls if the CHI interrupt line is asserted when the CHIF flag is set. 0 Disable interrupt line 1 Enable interrupt line Wakeup Interrupt Enable -- This flag controls if the wakeup interrupt line is asserted when the WUPIF flag is set. 0 Disable interrupt line 1 Enable interrupt line Receive FIFO channel B Not Empty Interrupt Enable -- This flag controls if the receive FIFO B interrupt line is asserted when the FNEBIF flag is set. 0 Disable interrupt line 1 Enable interrupt line Receive FIFO channel A Not Empty Interrupt Enable -- This flag controls if the receive FIFO A interrupt line is asserted when the FNEAIF flag is set. 0 Disable interrupt line 1 Enable interrupt line
9 RBIF
8 TBIF
7 MIE 6 PRIE 5 CHIE 4 WUPIE
3 FNEBIE
2 FNEAIE
MFR4300 Data Sheet, Rev. 3 78 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-16. GIFER Field Descriptions (Sheet 3 of 3)
Field 1 RBIE Description Receive Buffer Interrupt Enable -- This flag controls if the receive buffer interrupt line is asserted when the RBIF flag is set. 0 Disable interrupt line 1 Enable interrupt line Transmit Interrupt Enable -- This flag controls if the transmit buffer interrupt line is asserted when the TBIF flag is set. 0 Disable interrupt line 1 Enable interrupt line
0 TBIE
3.3.2.11
0x0018
15
Protocol Interrupt Flag Register 0 (PIFR0)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBVB_IF
LTXB_IF
LTXA_IF
MOC_IF
MRC_IF
FATL_IF
MXS_IF
ILCF_IF
INTL_IF
MTX_IF
CSA_IF
W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-10. Protocol Interrupt Flag Register 0 (PIFR0)
The register holds one set of the protocol related individual interrupt flags. The application clears an interrupt flag by writing a '1' to it. Writing a `0' will not change the state of the flag. If the application tries to clear a flag and the FlexRay module sets this flag at the same xtime, then that flag remains set.
Table 3-17. PIFR0 Field Descriptions (Sheet 1 of 3)
Field 15 FATL_IF Description Fatal Protocol Error Interrupt Flag -- This flag is set when the protocol engine has detected a fatal protocol error. In this case, the protocol engine goes into the POC:halt state immediately. The fatal protocol errors are: 1) pLatestTx violation, as described in the MAC process of the FlexRay protocol 2) transmission across slot boundary violation, as described in the FSP process of the FlexRay protocol 0 No such event. 1 Fatal protocol error detected. Internal Protocol Error Interrupt Flag -- This flag is set when the protocol engine has detected an internal protocol error. In this case, the protocol engine goes into the POC:halt state immediately. An internal protocol error occurs when the protocol engine has not finished a calculation and a new calculation is requested. This can be caused by a hardware error. 0 No such event. 1 Internal protocol error detected. Illegal Protocol Configuration Interrupt Flag -- This flag is set when the protocol engine has detected an illegal protocol configuration parameter setting. In this case, the protocol engine goes into the POC:halt state immediately. The protocol engine checks the listen_timeout value programmed into the Protocol Configuration Register 14 (PCR14) and Protocol Configuration Register 15 (PCR15) when the CONFIG_COMPLETE command was sent by the application via the Protocol Operation Control Register (POCR). If the value of listen_timeout is equal to zero, the protocol configuration setting is considered as illegal. 0 No such event. 1 Illegal protocol configuration detected.
14 INTL_IF
13 ILCF_IF
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 79
CYS_IF 0
CCL_IF
TI2_IF
TI1_IF
R
TBVA_IF
FlexRay Module (FLEXRAYV2)
Table 3-17. PIFR0 Field Descriptions (Sheet 2 of 3)
Field 12 CSA_IF Description Cold Start Abort Interrupt Flag -- This flag is set when the configured number of allowed cold start attempts is reached and none of these attempts was successful. The number of allowed cold start attempts is configured by the coldstart_attempts field in the Protocol Configuration Register 0 (PCR0). 0 No such event. 1 Cold start aborted and no more coldstart attempts allowed. Missing Rate Correction Interrupt Flag -- This flag is set when an insufficient number of measurements is available for rate correction at the end of the communication cycle. 0 No such event 1 Insufficient number of measurements for rate correction detected Missing Offset Correction Interrupt Flag -- This flag is set when an insufficient number of measurements is available for offset correction. This is related to the MISSING_TERM event in the CSP process for offset correction in the FlexRay protocol. 0 No such event. 1 Insufficient number of measurements for offset correction detected. Clock Correction Limit Reached Interrupt Flag -- This flag is set when the internal calculated offset or rate calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out field in the Protocol Configuration Register 9 (PCR9) and the rate_correction_out field in the Protocol Configuration Register 14 (PCR14). 0 No such event. 1 Offset or rate correction limit reached. Max Sync Frames Detected Interrupt Flag -- This flag is set when the number of synchronization frames detected in the current communication cycle exceeds the value of the node_sync_max field in the Protocol Configuration Register 30 (PCR30). 0 No such event. 1 More than node_sync_max sync frames detected. Note: Only synchronization frames that have passed the synchronization frame acceptance and rejection filters are taken into account. Media Access Test Symbol Received Interrupt Flag -- This flag is set when the MTS symbol was received on channel A or channel B. 0 No such event. 1 MTS symbol received. pLatestTx Violation on Channel B Interrupt Flag -- This flag is set when the frame transmission on channel B in the dynamic segment exceeds the dynamic segment boundary. This is related to the pLatestTx violation, as described in the MAC process of the FlexRay protocol. 0 No such event. 1 pLatestTx violation occurred on channel B. pLatestTx Violation on Channel A Interrupt Flag -- This flag is set when the frame transmission on channel A in the dynamic segment exceeds the dynamic segment boundary. This is related to the pLatestTx violation as described in the MAC process of the FlexRay protocol. 0 No such event. 1 pLatestTx violation occurred on channel A. Transmission across boundary on channel B Interrupt Flag -- This flag is set when the frame transmission on channel B crosses the slot boundary. This is related to the transmission across slot boundary violation as described in the FSP process of the FlexRay protocol. 0 No such event. 1 Transmission across boundary violation occurred on channel B.
11 MRC_IF
10 MOC_IF
9 CCL_IF
8 MXS_IF
7 MTX_IF
6 LTXB_IF
5 LTXA_IF
4 TBVB_IF
MFR4300 Data Sheet, Rev. 3 80 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-17. PIFR0 Field Descriptions (Sheet 3 of 3)
Field 3 TBVA_IF Description Transmission across boundary on channel A Interrupt Flag -- This flag is set when the frame transmission on channel A crosses the slot boundary. This is related to the transmission across slot boundary violation as described in the FSP process of the FlexRay protocol. 0 No such event. 1 Transmission across boundary violation occurred on channel A. Timer 2 Expired Interrupt Flag -- This flag is set whenever timer 2 expires. 0 No such event. 1 Timer 2 has reached its time limit. Timer 1 Expired Interrupt Flag -- This flag is set whenever timer 1 expires. 0 No such event 1 Timer 1 has reached its time limit Cycle Start Interrupt Flag -- This flag is set when a communication cycle starts. 0 No such event 1 Communication cycle started.
2 TI2_IF 1 TI1_IF 0 CYS_IF
3.3.2.12
0x001A
15
Protocol Interrupt Flag Register 1 (PIFR1)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMC_IF
SSI3_IF
SSI2_IF
SSI1_IF
SSI0_IF
W Reset
0
0
0
0
0
0
0
0
0
0
0
ODT_IF
PSC_IF
EVT_IF
IPC_IF
R
PECF_IF
0
0
0
0
0
0
0
0
0
0
0
Figure 3-11. Protocol Interrupt Flag Register 1 (PIFR1)
The register holds one set of the protocol related individual interrupt flags. The application clears an interrupt flag by writing a `1' to it. Writing `0' will not change the state of the flag. If the application clears a flag while the FlexRay module sets this flag at the same time, then that flag remains set.
Table 3-18. PIFR1 Field Descriptions (Sheet 1 of 2)
Field 15 EMC_IF Description Error Mode Changed Interrupt Flag -- This flag is set when the value of the ERRMODE bit field in the Protocol Status Register 0 (PSR0) is changed by the FlexRay module. 0 No such event. 1 ERRMODE field changed. Illegal Protocol Control Command Interrupt Flag -- This flag is set when the PE tries to execute a protocol control command, which was issued via the POCCMD field of the Protocol Operation Control Register (POCR), and detects that this protocol control command is not allowed in the current protocol state. In this case the command is not executed. For more details, see Section 3.6.2, "Protocol Control Command Execution". 0 No such event. 1 Illegal protocol control command detected. Protocol Engine Communication Failure Interrupt Flag -- This flag is set if the FlexRay module has detected a communication failure between the protocol engine and the controller host interface 0 No such event. 1 Protocol Engine Communication Failure detected.
14 IPC_IF
13 PECF_IF
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 81
FlexRay Module (FLEXRAYV2)
Table 3-18. PIFR1 Field Descriptions (Sheet 2 of 2)
Field 12 PSC_IF Description Protocol State Changed Interrupt Flag -- This flag is set when the protocol state in the PROTSTATE field in the Protocol Status Register 0 (PSR0) has changed. 0 No such event. 1 Protocol state changed. Slot Status Counter Incremented Interrupt Flag -- Each of these flags is set when the SLOTSTATUSCNT field in the corresponding Slot Status Counter Registers (SSCR0-SSCR3) is incremented. 0 No such event. 1 The corresponding slot status counter has incremented. Even Cycle Table Written Interrupt Flag -- This flag is set if the FlexRay module has written the sync frame measurement / ID tables into the FRM for the even cycle. 0 No such event. 1 Sync frame measurement table written Odd Cycle Table Written Interrupt Flag -- This flag is set if the FlexRay module has written the sync frame measurement / ID tables into the FRM for the odd cycle. 0 No such event. 1 Sync frame measurement table written
11-8 SSI[3:0]_IF
5 EVT_IF
4 ODT_IF
3.3.2.13
0x001C
15
Protocol Interrupt Enable Register 0 (PIER0)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBVB_IE
MOC_IE
MRC_IE
FATL_IE
MXS_IE
INTL_IE
ILCF_IE
MTX_IE
CSA_IE
W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-12. Protocol Interrupt Enable Register 0 (PIER0)
This register defines whether the interrupt flags defined in the Protocol Interrupt Flag Register 0 (PIFR0) can generate a interrupt request.
Table 3-19. PIER0 Field Descriptions
Field 15 FATL_IE 14 INTL_IE 13 ILCF_IE 12 CSA_IE 11 MRC_IE Description Fatal Protocol Error Interrupt Enable -- This bit controls FATL_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Internal Protocol Error Interrupt Enable -- This bit controls INTL_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Illegal Protocol Configuration Interrupt Enable -- This bit controls ILCF_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Cold Start Abort Interrupt Enable -- This bit controls CSA_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Missing Rate Correction Interrupt Enable -- This bit controls MRC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled MFR4300 Data Sheet, Rev. 3 82 Freescale Semiconductor
CYS_IE 0
CCL_IE
TI2_IE
TI1_IE
R
TBVA_IE
LTXB_IE
LTXA_IE
FlexRay Module (FLEXRAYV2)
Table 3-19. PIER0 Field Descriptions (Continued)
Field 10 MOC_IE 9 CCL_IE 8 MXS_IE 7 MTX_IE Description Missing Offset Correction Interrupt Enable -- This bit controls MOC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Clock Correction Limit Reached Interrupt Enable -- This bit controls CCL_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Max Sync Frames Detected Interrupt Enable -- This bit controls MXS_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Media Access Test Symbol Received Interrupt Enable -- This bit controls MTX_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled pLatestTx Violation on Channel B Interrupt Enable -- This bit controls LTXB_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled pLatestTx Violation on Channel A Interrupt Enable -- This bit controls LTXA_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Transmission across boundary on channel B Interrupt Enable -- This bit controls TBVB_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Transmission across boundary on channel A Interrupt Enable -- This bit controls TBVA_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Timer 2 Expired Interrupt Enable -- This bit controls TI1_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Timer 1 Expired Interrupt Enable -- This bit controls TI1_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Cycle Start Interrupt Enable -- This bit controls CYC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled
6 LTXB_IE 5 LTXA_IE 4 TBVB_IE
3 TBVA_IE
2 TI2_IE 1 TI1_IE 0 CYS_IE
3.3.2.14
0x001E
15
Protocol Interrupt Enable Register 1 (PIER1)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMC_IE
SSI3_IE
SSI2_IE
SSI1_IE
SSI0_IE
W Reset
0
0
0
0
0
0
0
0
0
0
0
ODT_IE
PSC_IE
EVT_IE
IPC_IE
R
PECF_IE
0
0
0
0
0
0
0
0
0
0
0
Figure 3-13. Protocol Interrupt Enable Register 1 (PIER1)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 83
FlexRay Module (FLEXRAYV2)
This register defines whether the interrupt flags defined in Protocol Interrupt Flag Register 1 (PIFR1) can generate a interrupt request.
Table 3-20. PIER1 Field Descriptions
Field 15 EMC_IE 14 IPC_IE 13 PECF_IE Description Error Mode Changed Interrupt Enable -- This bit controls EMC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Illegal Protocol Control Command Interrupt Enable -- This bit controls IPC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Protocol Engine Communication Failure Interrupt Enable -- This bit controls PECF_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Protocol State Changed Interrupt Enable -- This bit controls PSC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Slot Status Counter Incremented Interrupt Enable -- This bit controls SSI[3:0]_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Even Cycle Table Written Interrupt Enable -- This bit controls EVT_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled Odd Cycle Table Written Interrupt Enable -- This bit controls ODT_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled
12 PSC_IE 11-8 SSI[3:0]_IE
5 EVT_IE 4 ODT_IE
3.3.2.15
0x0020
15
CHI Error Flag Register (CHIERFR)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMI_EF
MBU_EF
NMF_EF 0
MBS_EF
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-14. CHI Error Flag Register (CHIERFR)
This register holds the CHI related error flags. The application can clear any error flag by writing a '1' to it. Writing a `0' will not change the state of the flag. If the application clears a flag while the FlexRay module sets the flag at the same time, then that flag remains set. The interrupt generation for each of these error flags is controlled by the CHI interrupt enable bit CHIE in the Global Interrupt Flag and Enable Register (GIFER).
MFR4300 Data Sheet, Rev. 3 84 Freescale Semiconductor
ILSA_EF 0
NML_EF
DBL_EF
DPL_EF
LCK_EF
SPL_EF
FID_EF
R
SBCF_EF
FOVB_EF
FOVA_EF
FRLB_EF
FRLA_EF
FlexRay Module (FLEXRAYV2)
Table 3-21. CHIERFR Field Descriptions (Sheet 1 of 2)
Field 15 FRLB_EF Description Frame Lost Channel B Error Flag -- This flag is set if a complete frame was received on channel B but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. In this case, the frame and the related slot status information are lost. 0 No such event 1 Frame lost on channel B detected Frame Lost Channel A Error Flag -- This flag is set if a complete frame was received on channel A but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. In this case, the frame and the related slot status information are lost. 0 No such error 1 Frame lost on channel A detected Protocol Command Ignored Error Flag -- This flag is set if the application has issued a POC command by writing to the POCCMD field in the Protocol Operation Control Register (POCR) while the BSY flag is equal to `1'. In this case the command is ignored by the FlexRay module and is lost. 0 No such error 1 POC command ignored Receive FIFO Overrun Channel B Error Flag -- This flag is set when an overrun of the Receive FIFO for channel B occurred. This error occurs if a semantically valid frame was received on channel B and matches the all criteria to be appended to the FIFO for channel B but the FIFO is full. In this case, the received frame and its related slot status information is lost. 0 No such error 1 Receive FIFO overrun on channel B has been detected Receive FIFO Overrun Channel A Error Flag -- This flag is set when an overrun of the Receive FIFO for channel A occurred. This error occurs if a semantically valid frame was received on channel A and matches the all criteria to be appended to the FIFO for channel A but the FIFO is full. In this case, the received frame and its related slot status information is lost. 0 No such error 1 Receive FIFO overrun on channel B has been detected Message Buffer Search Error Flag -- This flag is set if the message buffer search engine is still running while the next search cycle must be started due to the FlexRay protocol timing. In this case, not all message buffers are considered while searching. 0 No such event 1 Search engine active while search start appears Message Buffer Utilization Error Flag -- This flag is asserted if the application writes to a message buffer control field that is beyond the number of utilized message buffers programmed in the Message Buffer Segment Size and Utilization Register (MBSSUTR). If the application writes to a MBCCSRn register with n > LAST_MB_UTIL, the FlexRay module ignores the write attempt and asserts the message buffer utilization error flag MBU_EF in the CHI Error Flag Register (CHIERFR). 0 No such event 1 Non-utilized message buffer enabled 8 LCK_EF Lock Error Flag -- This flag is set if the application tries to lock a message buffer that is already locked by the FlexRay module due to internal operations. In that case, the FlexRay module does not grant the lock to the application. The application must issue the lock request again. 0 No such error 1 Lock error detected Double Transmit Message Buffer Lock Error Flag -- This flag is set if the application tries to lock the transmit side of a double transmit message buffer. In this case, the FlexRay module does not grant the lock to the transmit side of a double transmit message buffer. 0 No such event 1 Double transmit buffer lock error occurred MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 85
14 FRLA_EF
13 PCMI_EF
12 FOVB_EF
11 FOVA_EF
10 MSB_EF
9 MBU_EF
7 DBL_EF
FlexRay Module (FLEXRAYV2)
Table 3-21. CHIERFR Field Descriptions (Sheet 2 of 2)
Field 6 SBCF_EF Description System Bus Communication Failure Error Flag -- This flag is set if the FlexRay module was not able to transmit or receive data via the system bus in time. In the case of writing, data is lost; in the case of reading, the transmission onto the FlexRay bus is stopped for the current slot and resumed in the next slot. 0 No such event 1 System bus communication failure occurred Frame ID Error Flag -- This flag is set if the frame ID stored in the message buffer header area differs from the frame ID stored in the message buffer control register. 0 No such error occurred 1 Frame ID error occurred Dynamic Payload Length Error Flag -- This flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payload length for the dynamic segment as it is configured in the corresponding protocol configuration register field max_payload_length_dynamic in the Protocol Configuration Register 24 (PCR24). 0 No such error occurred 1 Dynamic payload length error occurred Static Payload Length Error Flag -- This flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the static segment is different from the payload length for the static segment as it is configured in the corresponding protocol configuration register field payload_length_static in the Protocol Configuration Register 19 (PCR19). 0 No such error occurred 1 Static payload length error occurred Network Management Length Error Flag -- This flag is set if the payload length written into the header structure of a receive message buffer assigned to the static segment is less than the configured length of the Network Management Vector as configured in the Network Management Vector Length Register (NMVLR). In this case the received part of the Network Management Vector will be used to update the Network Management Vector. 0 No such error occurred 1 Network management length error occurred Network Management Frame Error Flag -- This flag is set if a received message in the static segment with a Preamble Indicator flag PP asserted has its Null Frame indicator flag NF asserted as well. In this case, the Global Network Management Registers (see Network Management Vector Registers (NMVR0-NMVR5)) are not updated. 0 No such error occurred 1 Network management frame error occurred Illegal System Memory Access Error Flag -- This flag is set if the external system memory subsystem has detected and indicated an illegal system memory access from the FlexRay module. The exact meaning of an illegal system memory access is defined by the current implementation of the memory subsystem. 0 No such event. 1 Illegal system memory access occurred.
5 FID_EF
4 DPL_EF
3 SPL_EF
2 NML_EF
1 NMF_EF
0 ILSA_EF
3.3.2.16
0x0022
15
Message Buffer Interrupt Vector Register (MBIVEC)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0 0 0 0
TBIVEC 0 0 0 0
0 0 0 0 0
RBIVEC 0 0 0 0
Figure 3-15. Message Buffer Interrupt Vector Register (MBIVEC)
MFR4300 Data Sheet, Rev. 3 86 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
This register indicates the lowest numbered receive message buffer and the lowest numbered transmit message buffer that have their interrupt status flag MBIF and interrupt enable MBIE bits asserted. This means that message buffers with lower message buffer numbers have higher priority.
Table 3-22. MBIVEC Field Descriptions
Field 14-8 TBIVEC Description Transmit Buffer Interrupt Vector -- This field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt status flag MBIF and its interrupt enable bit MBIE set. If there is no transmit message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this field is set to 0. Receive Buffer Interrupt Vector -- This field provides the message buffer number of the lowest numbered receive message buffer which has its interrupt flag MBIF and its interrupt enable bit MBIE asserted. If there is no receive message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this field is set to 0.
6-0 RBIVEC
3.3.2.17
0x0024
15
Channel A Status Error Counter Register (CASERCR)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
STATUS_ERR_CNT 0 0 0 0 0 0 0 0 0
Figure 3-16. Channel A Status Error Counter Register (CASERCR)
This register provides the channel status error counter for channel A. The protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector contains the four protocol related error indicator bits vSS!SyntaxError, vSS!ContentError, vSS!BViolation, and vSS!TxConflict. The FlexRay module increments the counter by 1 if, for a slot or segment, at least one error indicator bit is set to `1'. The counter wraps around after it has reached the maximum value. For more information on slot status monitoring, see Section 3.4.18, "Slot Status Monitoring".
Table 3-23. CASERCR Field Descriptions
Field Description
15-0 Channel Status Error Counter -- This field provides the current value channel status error counter. The STATUS_ERR_CNT counter value is updated within the first macrotick of the following slot or segment.
3.3.2.18
0x0026
15
Channel B Status Error Counter Register (CBSERCR)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
STATUS_ERR_CNT 0 0 0 0 0 0 0 0 0
Figure 3-17. Channel B Status Error Counter Register (CBSERCR)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 87
FlexRay Module (FLEXRAYV2)
This register provides the channel status error counter for channel B. The protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector contains the four protocol related error indicator bits vSS!SyntaxError, vSS!ContentError, vSS!BViolation, and vSS!TxConflict. The FlexRay module increments the counter by 1 if, for a slot or segment, at least one error bit is set to `1'. The counter wraps around after it has reached the maximum value. For more information on slot status monitoring see Section 3.4.18, "Slot Status Monitoring".
Table 3-24. CBSERCR Field Descriptions
Field Description
15-0 Channel Status Error Counter -- This field provides the current channel status error count. The counter STATUS_ERR_CNT value is updated within the first macrotick of the following slot or segment.
3.3.2.19
0x0028
15
Protocol Status Register 0 (PSR0)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ERRMODE W Reset 0 0
SLOTMODE 0 0
0 0 0
PROTSTATE 0 0 0
STARTUPSTATE 0 0 0
0 0
WAKEUPSTATUS 0 0 0
Figure 3-18. Protocol Status Register 0 (PSR0)
This register provides information about the current protocol status.
Table 3-25. PSR0 Field Descriptions (Sheet 1 of 2)
Field 15-14 ERRMODE Description Error Mode -- protocol related variable: vPOC!ErrorMode. This field indicates the error mode of the protocol. 00 ACTIVE 01 PASSIVE 10 COMM_HALT 11 reserved
13-12 Slot Mode -- protocol related variable: vPOC!SlotMode. This field indicates the slot mode of the protocol. SLOTMODE 00 SINGLE 01 ALL_PENDING 10 ALL 11 reserved 10-8 Protocol State -- protocol related variable: vPOC!State. This field indicates the state of the protocol. PROTSTATE 000 POC:default config 001 POC:config 010 POC:wakeup 011 POC:ready 100 POC:normal passive 101 POC:normal active 110 POC:halt 111 POC:startup
MFR4300 Data Sheet, Rev. 3 88 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-25. PSR0 Field Descriptions (Sheet 2 of 2)
Field 7-4 STARTUP STATE Description Startup State -- protocol related variable: vPOC!StartupState. This field indicates the current sub-state of the startup procedure. 0000 reserved 0001 reserved 0010 POC:coldstart collision resolution 0011 POC:coldstart listen 0100 POC:integration consistency check 0101 POC:integrationi listen 0110 reserved 0111 POC:initialize schedule 1000 reserved 1001 reserved 1010 POC:coldstart consistency check 1011 reserved 1100 reserved 1101 POC:integration coldstart check 1110 POC:coldstart gap 1111 POC:coldstart join Wakeup Status -- protocol related variable: vPOC!WakeupStatus. This field provides the outcome of the execution of the wakeup mechanism. 000 reserved 001 RECEIVED_HEADER 010 RECEIVED_WUP 011 COLLISION_HEADER 100 COLLISION_WUP 101 COLLISION_UNKNOWN 110 TRANSMITTED 111 reserved
2-0 WAKEUP STATUS
3.3.2.20
0x002A
15
Protocol Status Register 1 (PSR1)
Additional Reset: CSAA, CSP, CPN: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3
Write: Normal Mode
2 1 0
R W Reset
CSAA 0
CSP 0
0 0 0 0
REMCSAT 0 0 0
CPN 0
HHR 0
FRZ 0 0 0
APTAC 0 0 0
Figure 3-19. Protocol Status Register 1 (PSR1)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 89
FlexRay Module (FLEXRAYV2)
Table 3-26. PSR1 Field Descriptions
Field 15 CSAA Description Cold Start Attempt Aborted Flag -- protocol related event: `set coldstart abort indicator in CHI' This flag bit is set when the FlexRay modulehas aborted a cold start attempt. The application clears this flag by writing 1 to it. Writing a 0 will not change the state of the flag. If the application clears the flag while the FlexRay module sets the flag at the same time, then the flag is not cleared. 0 No such event 1 Cold start attempt aborted Leading Cold Start Path -- This status bit is set when the FlexRay module has reached the POC:normal active state via the leading cold start path. This indicates that this node has started the network 0 No such event 1 POC:normal active reached from POC:startup state via leading cold start path Remaining Coldstart Attempts -- protocol related variable: vRemainingColdstartAttempts This field provides the number of remaining cold start attempts that the FlexRay module will execute. Leading Cold Start Path Noise -- protocol related variable: vPOC!ColdstartNoise This status bit is set if the FlexRay module has reached the POC:normal active state via the leading cold start path under noise conditions. This indicates there was some activity on the FlexRay bus while the FlexRay module was starting up the cluster. 0 No such event 1 POC:normal active state was reached from POC:startup state via noisy leading cold start path Host Halt Request Pending -- protocol related variable: vPOC!CHIHaltRequest This status bit is set when FlexRay module receives the HALT command from the application via the Protocol Operation Control Register (POCR). The FlexRay module clears this status bit after a hard reset condition or when the protocol is in the POC:default config state. 0 No such event 1 HALT command received Freeze Occurred -- protocol related variable: vPOC!Freeze This status bit is set when the FlexRay module has reached the POC:halt state due to the host FREEZE command or due to an internal error condition requiring immediate halt. The FlexRay module clears this status bit after a hard reset condition or when the protocol is in the POC:default config state. 0 No such event 1 Immediate halt due to FREEZE or internal error condition Allow Passive to Active Counter -- protocol related variable: vPOC!AllowPassivetoActive This field provides the number of consecutive even/odd communication cycle pairs that have passed with valid rate and offset correction terms, but the protocol is still in the POC:normal passive state due to an application configured delay to enter POC:normal active state. This delay is defined by the allow_passive_to_active field in the Protocol Configuration Register 12 (PCR12). If this APTAC counter has reached its maximum value, it is not incremented any more.
14 CSP
12-8 REMCSAT 7 CPN
6 HHR
5 FRZ
4-0 APTAC
3.3.2.21
0x002C
15
Protocol Status Register 2 (PSR2)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NBVB NSEB STCB SBVB SSEB MTB NBVA NSEA STCA SBVA SSEA MTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
CLKCORRFAILCNT 0 0 0
Figure 3-20. Protocol Status Register 2 (PSR2)
This register provides a snapshot of status information about the Network Idle Time NIT, the Symbol Window and the clock synchronization. The NIT related status bits NBVB, NSEB, NBVA, and NSEA are
MFR4300 Data Sheet, Rev. 3 90 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
updated by the FlexRay module after the end of the NIT and before the end of the first slot of the next communication cycle. The Symbol Window related status bits STCB, SBVB, SSEB, MTB, STCA, SBVA, SSEB, and MTA are updated by the FlexRay module after the end of the symbol window and before the end of the current communication cycle. If no symbol window is configured, the symbol window related status bits remain in their reset state. The clock synchronization related CLKCORRFAILCNT is updated by the FlexRay module after the end of the static segment and before the end of the current communication cycle.
Table 3-27. PSR2 Field Descriptions (Sheet 1 of 2)
Field 15 NBVB Description NIT Boundary Violation on Channel B -- protocol related variable: vSS!BViolation for NIT on channel B This status bit is set when there was some media activity on the FlexRay bus channel B at the end of the NIT. 0 No such event 1 Media activity at boundaries detected NIT Syntax Error on Channel B -- protocol related variable: vSS!SyntaxError for NIT on channel B This status bit is set when a syntax error was detected during NIT on channel B. 0 No such event 1 Syntax error detected Symbol Window Transmit Conflict on Channel B -- protocol related variable: vSS!TxConflict for symbol window on channel B This status bit is set if there was a transmission conflict during the symbol window on channel B. 0 No such event 1 Transmission conflict detected Symbol Window Boundary Violation on Channel B -- protocol related variable: vSS!BViolation for symbol window on channel B This status bit is set if there was some media activity on the FlexRay bus channel B at the start or at the end of the symbol window. 0 No such event 1 Media activity at boundaries detected Symbol Window Syntax Error on Channel B -- protocol related variable: vSS!SyntaxError for symbol window on channel B This status bit is set when a syntax error was detected during the symbol window on channel B. 0 No such event 1 Syntax error detected Media Access Test Symbol MTS Received on Channel B -- protocol related variable: vSS!ValidMTS for Symbol Window on channel B This status bit is set if the Media Access Test Symbol MTS was received in the symbol window on channel B. 0 No such event 1 MTS symbol received NIT Boundary Violation on Channel A -- protocol related variable: vSS!BViolation for NIT on channel A This status bit is set when there was some media activity on the FlexRay bus channel A at the end of the NIT. 0 No such event 1 Media activity at boundaries detected NIT Syntax Error on Channel A -- protocol related variable: vSS!SyntaxError for NIT on channel A This status bit is set when a syntax error was detected during NIT on channel A. 0 No such event 1 Syntax error detected
14 NSEB
13 STCB
12 SBVB
11 SSEB
10 MTB
9 NBVA
8 NSEA
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 91
FlexRay Module (FLEXRAYV2)
Table 3-27. PSR2 Field Descriptions (Sheet 2 of 2)
Field 7 STCA Description Symbol Window Transmit Conflict on Channel A -- protocol related variable: vSS!TxConflict for symbol window on channel A This status bit is set if there was a transmission conflicts during the symbol window on channel A. 0 No such event 1 Transmission conflict detected Symbol Window Boundary Violation on Channel A -- protocol related variable: vSS!BViolation for symbol window on channel A This status bit is set if there was some media activity on the FlexRay bus channel A at the start or at the end of the symbol window. 0 No such event 1 Media activity at boundaries detected Symbol Window Syntax Error on Channel A -- protocol related variable: vSS!SyntaxError for symbol window on channel A This status bit is set when a syntax error was detected during the symbol window on channel A. 0 No such event 1 Syntax error detected Media Access Test Symbol MTS Received on Channel A -- protocol related variable: vSS!ValidMTS for symbol window on channel A This status bit is set if the Media Access Test Symbol MTS was received in the symbol window on channel A. 1 MTS symbol received 0 No such event Clock Correction Failed Counter -- protocol related variable: vClockCorrectionFailed This field provides the number of consecutive even/odd communication cycle pairs that have passed without clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. It is not incremented when it has reached the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the Protocol Configuration Register 8 (PCR8). The FlexRay module resets this counter on a hard reset condition, when the protocol enters the POC:normal active state, or when both the rate and offset correction terms have been calculated successfully.
6 SBVA
5 SSEA
4 MTA
3-0 CLKCORRFAILCNT
3.3.2.22
0x002E
15
Protocol Status Register 3 (PSR3)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3
Write: Normal Mode
2 1 0
R W Reset
0 0
0 0
WUB ABVB AACB ACEB ASEB AVFB 0 0 0 0 0 0
0 0
0 0
WUA ABVA AACA ACEA ASEA AVFA 0 0 0 0 0 0
Figure 3-21. Protocol Status Register 3 (PSR3)
This register provides aggregated channel status information as an accrued status of channel activity for all communication slots, regardless of whether they are assigned for transmission or subscribed for reception. It provides accrued information for the symbol window, the NIT, and the wakeup status. The application can clear any flag at any time by writing a '1' to it. Writing a `0' will not change the flag state. If the application tries to clear a flag while the FlexRay module sets the flag at the same time, then that flag is not cleared.
MFR4300 Data Sheet, Rev. 3 92 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-28. PSR3 Field Descriptions (Sheet 1 of 2)
Field 13 WUB Description Wakeup Symbol Received on Channel B -- This flag is set when a wakeup symbol was received on channel B. 0 No wakeup symbol received 1 Wakeup symbol received Aggregated Boundary Violation on Channel B -- This flag is set when a boundary violation has been detected on channel B. Boundary violations are detected in the communication slots, the symbol window, and the NIT. 0 No boundary violation detected 1 Boundary violation detected Aggregated Additional Communication on Channel B -- This flag is set when at least one valid frame was received on channel B in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 No additional communication detected 1 Additional communication detected Aggregated Content Error on Channel B -- This flag is set when a content error has been detected on channel B. Content errors are detected in the communication slots, the symbol window, and the NIT. 0 No content error detected 1 Content error detected Aggregated Syntax Error on Channel B -- This flag is set when a syntax error has been detected on channel B. Syntax errors are detected in the communication slots, the symbol window and the NIT. 0 No syntax error detected 1 Syntax errors detected Aggregated Valid Frame on Channel B -- This flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel B. 1 At least one syntactically valid frame received 0 No syntactically valid frames received Wakeup Symbol Received on Channel A -- This flag is set when a wakeup symbol was received on channel A. 0 No wakeup symbol received 1 Wakeup symbol received Aggregated Boundary Violation on Channel A -- This flag is set when a boundary violation has been detected on channel A. Boundary violations are detected in the communication slots, the symbol window, and the NIT. 0 No boundary violation detected 1 Boundary violation detected Aggregated Additional Communication on Channel A -- This flag is set when a valid frame was received in a slot on channel A that also contained an additional communication with either syntax error, content error, or boundary violations. 0 No additional communication detected 1 Additional communication detected Aggregated Content Error on Channel A -- This flag is set when a content error has been detected on channel A. Content errors are detected in the communication slots, the symbol window, and the NIT. 0 No content error detected 1 Content error detected
12 ABVB
11 AACB
10 ACEB
9 ASEB
8 AVFB
5 WUA
4 ABVA
3 AACA
2 ACEA
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 93
FlexRay Module (FLEXRAYV2)
Table 3-28. PSR3 Field Descriptions (Sheet 2 of 2)
Field 1 ASEA Description Aggregated Syntax Error on Channel A -- This flag is set when a syntax error has been detected on channel A. Syntax errors are detected in the communication slots, the symbol window, and the NIT. 0 No syntax error detected 1 Syntax errors detected Aggregated Valid Frame on Channel A -- This flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel A. 0 No syntactically valid frames received 1 At least one syntactically valid frame received
0 AVFA
3.3.2.23
0x0030
15
Macrotick Counter Register (MTCTR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0 0 0 0 0 0 0
MTCT 0 0 0 0 0 0 0 0
Figure 3-22. Macrotick Counter Register (MTCTR)
This register provides the macrotick count of the current communication cycle.
Table 3-29. MTCTR Field Descriptions
Field 13-0 MTCT Description Macrotick Counter -- protocol related variable: vMacrotick This field provides the macrotick count of the current communication cycle.
3.3.2.24
0x0032
15
Cycle Counter Register (CYCTR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0
CYCCNT 0 0 0 0
Figure 3-23. Cycle Counter Register (CYCTR)
This register provides the number of the current communication cycle.
Table 3-30. CYCTR Field Descriptions
Field 5-0 CYCCNT Description Cycle Counter -- protocol related variable: vCycleCounter This field provides the number of the current communication cycle. If the counter reaches the maximum value of 63, the counter wraps and starts from zero again.
MFR4300 Data Sheet, Rev. 3 94 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.25
0x0034
15
Slot Counter Channel A Register (SLTCTAR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0
SLOTCNTA 0 0 0 0 0 0
Figure 3-24. Slot Counter Channel A Register (SLTCTAR)
This register provides the number of the current slot in the current communication cycle for channel A.
Table 3-31. SLTCTAR Field Descriptions
Field 10-0 SLOTCNTA Description Slot Counter Value for Channel A -- protocol related variable: vSlotCounter for channel A This field provides the number of the current slot in the current communication cycle.
3.3.2.26
0x0036
15
Slot Counter Channel B Register (SLTCTBR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0
SLOTCNTB 0 0 0 0 0 0
Figure 3-25. Slot Counter Channel B Register (SLTCTBR)
This register provides the number of the current slot in the current communication cycle for channel B.
Table 3-32. SLTCTBR Field Descriptions
Field 10-0 SLOTCNTA Description Slot Counter Value for Channel B -- protocol related variable: vSlotCounter for channel B This field provides the number of the current slot in the current communication cycle.
3.3.2.27
0x0038
15
Rate Correction Value Register (RTCORVR)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
RATECORR 0 0 0 0 0 0 0 0 0
Figure 3-26. Rate Correction Value Register (RTCORVR)
This register provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. The FlexRay module updates this register during the NIT of each odd numbered communication cycle.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 95
FlexRay Module (FLEXRAYV2)
Table 3-33. RTCORVR Field Descriptions
Field Description
15-0 Rate Correction Value -- protocol related variable: vRateCorrection (before value limitation and external rate RATECORR correction) This field provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. The value is represented in 2's complement format. This value does not include the value limitation and the application of the external rate correction. If the magnitude of the internally calculated rate correction value exceeds the limit given by rate_correction_out in the Protocol Configuration Register 13 (PCR13), the clock correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register 0 (PIFR0). Note: If the FlexRay module was not able to calculate a new rate correction term due to a lack of synchronization frames, the RATECORR value is not updated.
3.3.2.28
0x003A
15
Offset Correction Value Register (OFCORVR)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
OFFSETCORR 0 0 0 0 0 0 0 0 0
Figure 3-27. Offset Correction Value Register (OFCORVR)
This register provides the sign extended offset correction value in microticks as it was calculated by the clock synchronization algorithm. The FlexRay module updates this register during the NIT.
Table 3-34. OFCORVR Field Descriptions
Field 15-0 OFFSETCORR Description Offset Correction Value -- protocol related variable: vOffsetCorrection (before value limitation and external offset correction) This field provides the sign extended offset correction value in microticks as it was calculated by the clock synchronization algorithm. The value is represented in 2's complement format. This value does not include the value limitation and the application of the external offset correction. If the magnitude of the internally calculated rate correction value exceeds the limit given by offset_correction_out field in the Protocol Configuration Register 29 (PCR29), the clock correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register 0 (PIFR0). Note: If the FlexRay module was not able to calculate an new offset correction term due to a lack of synchronization frames, the OFFSETCORR value is not updated.
3.3.2.29
0x003C
15
Combined Interrupt Flag Register (CIFRR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNEBIF
0 W Reset 0
0
0
0
0
0
0
0
MIF
PRIF
CHIF
WUPIF
R
FNEAIF
RBIF
TBIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-28. Combined Interrupt Flag Register (CIFRR)
MFR4300 Data Sheet, Rev. 3 96 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
This register provides five combined interrupt flags and a copy of three individual interrupt flags. The combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in Figure 3-143. The individual interrupt flags WUPIF, FNEBIF, and FNEAIF are copies of corresponding flags in the Global Interrupt Flag and Enable Register (GIFER) and are provided here to simplify the application interrupt flag check. To clear the individual interrupt flags, the application must use the Global Interrupt Flag and Enable Register (GIFER). NOTE The meanings of the five combined status bits MIF, PRIF, CHIF, RBIF, and TBIF are different from those mentioned in the Global Interrupt Flag and Enable Register (GIFER).
Table 3-35. CIFRR Field Descriptions
Field 7 MIF Description Module Interrupt Flag -- This flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 No interrupt source has its interrupt flag asserted 1 At least one interrupt source has its interrupt flag asserted Protocol Interrupt Flag -- This flag is set if at least one of the individual protocol interrupt flags in the Protocol Interrupt Flag Register 0 (PIFR0) or Protocol Interrupt Flag Register 1 (PIFR1) is equal to 1. 0 All individual protocol interrupt flags are equal to 0 1 At least one of the individual protocol interrupt flags is equal to 1 CHI Interrupt Flag -- This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register (CHIERFR) is equal to 1. 0 All CHI error flags are equal to 0 1 At least one CHI error flag is equal to 1 Wakeup Interrupt Flag -- Copy of GIFER.WUPIF Receive FIFO channel B Not Empty Interrupt Flag -- Copy of GIFER.FNEBIF Receive FIFO channel A Not Empty Interrupt Flag -- Copy of GIFER.FNEAIF Receive Message Buffer Interrupt Flag -- This flag is set if for at least one of the individual receive message buffers (MBCCSn.MTD = 0) the interrupt flag MBIF in the corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) is equal to 1. 0 None of the individual receive message buffers has the MBIF flag asserted. 1 At least one individual receive message buffers has the MBIF flag asserted. Transmit Message Buffer Interrupt Flag -- This flag is set if for at least one of the individual single or double transmit message buffers (MBCCSn.MTD = 1) the interrupt flag MBIF in the corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) is equal to 1. 0 None of the individual transmit message buffers has the MBIF flag asserted. 1 At least one individual transmit message buffers has the MBIF flag asserted.
6 PRIF
5 CHIF
4 WUPIF 3 FNEBIF 2 FNEAIF 1 RBIF
0 TBIF
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 97
FlexRay Module (FLEXRAYV2)
3.3.2.30
0x0040
15
Sync Frame Counter Register (SFCNTR)
Additional Reset: RUN Command
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0
SFEVB 0 0 0 0
SFEVA 0 0 0 0
SFODB 0 0 0 0
SFODA 0 0 0
Figure 3-29. Sync Frame Counter Register (SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the last even and in the last odd numbered communication cycle. This register is updated after the NIT start and before 10 MT after offset correction start. NOTE If the application has locked the even synchronization table at the end of the static segment of an even communication cycle, the FlexRay module will not update the fields SFEVB and SFEVA. If the application has locked the odd synchronization table at the end of the static segment of an odd communication cycle, the FlexRay module will not update the values SFODB and SFODA.
Table 3-36. SFCNTR Field Descriptions
Field 15-12 SFEVB 11-8 SFEVB 7-4 SFODB 3-0 SFODA Description Sync Frames Channel B, even cycle -- protocol related variable: size of (vsSyncIdListB for even cycle) This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization. Sync Frames Channel A, even cycle -- protocol related variable: size of (vsSyncIdListA for even cycle) This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization. Sync Frames Channel B, odd cycle -- protocol related variable: size of (vsSyncIdListB for odd cycle) This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization. Sync Frames Channel A, odd cycle -- protocol related variable: size of (vsSyncIdListA for odd cycle) This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization.
3.3.2.31
0x0042
15
Sync Frame Table Offset Register (SFTOR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0
SFT_OFFSET[15:1] 0 0 0 0 0 0 0 0 0
0 0
Figure 3-30. Sync Frame Table Offset Register (SFTOR)
This register defines the FRM related offset for Sync Frame Tables. For more details, see Section 3.4.12, "Sync Frame ID and Sync Frame Deviation Tables".
MFR4300 Data Sheet, Rev. 3 98 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-37. SFTOR Field Description
Field 15-1 SFTOR Description Sync Frame Table Offset -- Offset of the Sync Frame Tables in the FRM. This offset is required to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.
3.3.2.32
0x0044
15
Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
Write: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W ELKT OLKT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
OPT 0
0
Figure 3-31. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
This register provides configuration, control, and status information related to the generation and access of the clock sync ID Tables and clock sync measurement tables. For a detailed description, see Section 3.4.12, "Sync Frame ID and Sync Frame Deviation Tables".
Table 3-38. SFTCCSR Field Descriptions (Sheet 1 of 2)
Field 15 ELKT 14 OLKT 13-8 CYCNUM 7 ELKS Description Even Cycle Tables Lock/Unlock Trigger -- This trigger bit is used to lock and unlock the even cycle tables. 0 No effect 1 Triggers lock/unlock of the even cycle tables. Odd Cycle Tables Lock/Unlock Trigger -- This trigger bit is used to lock and unlock the odd cycle tables. 0 No effect 1 Triggers lock/unlock of the odd cycle tables. Cycle Number -- This field provides the number of the cycle in which the currently locked table was recorded. If none or both tables are locked, this value is related to the even cycle table. Even Cycle Tables Lock Status -- This status bit indicates whether the application has locked the even cycle tables. 0 Application has not locked the even cycle tables. 1 Application has locked the even cycle tables. Odd Cycle Tables Lock Status -- This status bit indicates whether the application has locked the odd cycle tables. 0 Application has not locked the odd cycle tables. 1 Application has locked the odd cycle tables. Even Cycle Tables Valid -- This status bit indicates whether the Sync Frame ID and Sync Frame Deviation Tables for the even cycle are valid. The FlexRay module clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 Tables are not valid (update is ongoing) 1 Tables are valid (consistent). Odd Cycle Tables Valid -- This status bit indicates whether the Sync Frame ID and Sync Frame Deviation Tables for the odd cycle are valid. The FlexRay module clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 Tables are not valid (update is ongoing) 1 Tables are valid (consistent).
6 OLKS
5 EVAL
4 OVAL
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 99
SIDEN 0
R
0
0
CYCNUM
ELKS OLKS EVAL OVAL
0
0
SDVEN
FlexRay Module (FLEXRAYV2)
Table 3-38. SFTCCSR Field Descriptions (Sheet 2 of 2)
Field 2 OPT Description One Pair Trigger -- This trigger bit controls whether the FlexRay module writes continuously or only one pair of Sync Frame Tables into the FRM. If this trigger is set to `1' while SDVEN or SIDEN is set to `1', the FlexRay module writes only one pair of the enabled Sync Frame Tables corresponding to the next even-odd-cycle pair into the FRM. In this case, the FlexRay module clears the SDVEN or SIDEN bits immediately. If this trigger is set to `0' while SDVEN or SIDEN is set to `1', the FlexRay module writes continuously the enabled Sync Frame Tables into the FRM. 0 Write continuously pairs of enabled Sync Frame Tables into FRM. 1 Write only one pair of enabled Sync Frame Tables into FRM. Sync Frame Deviation Table Enable -- This bit controls the generation of the Sync Frame Deviation Tables. The application must set this bit to request the FlexRay module to write the Sync Frame Deviation Tables into the FRM. 0 Do not write Sync Frame Deviation Tables 1 Write Sync Frame Deviation Tables into FRM Note: If the application sets SDVEN to `1', then the application must set SIDEN to `1' too. Sync Frame ID Table Enable -- This bit controls the generation of the Sync Frame ID Tables. The application must set this bit to `1' to request the FlexRay module to write the Sync Frame ID Tables into the FRM. 0 Do not write Sync Frame ID Tables 1 Write Sync Frame ID Tables into FRM
1 SDVEN
0 SIDEN
3.3.2.33
0x0046
15
Sync Frame ID Rejection Filter Register (SFIDRFR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5 4 3
Write: Normal Mode
2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0
SYNFRID 0 0 0 0 0 0
Figure 3-32. Sync Frame ID Rejection Filter Register (SFIDRFR)
This register defines the Sync Frame Rejection Filter ID. The application must update this register outside of the static segment. If the application updates this register in the static segment, it can appear that the FlexRay module accepts the sync frame in the current cycle.
Table 3-39. SFIDRFR Field Descriptions
Field 9-0 SYNFRID Description Sync Frame Rejection ID -- This field defines the frame ID of a frame that must not be used for clock synchronization. For details see Section 3.4.15.2, "Sync Frame Rejection Filtering".
MFR4300 Data Sheet, Rev. 3 100 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.34
0x0048
15
Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0
FVAL 0 0 0 0 0
Figure 3-33. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
This register defines the sync frame acceptance filter value. For details on filtering, see Section 3.4.15, "Sync Frame Filtering".
Table 3-40. SFIDAFVR Field Descriptions
Field 9-0 FVAL Description Filter Value -- This field defines the value for the sync frame acceptance filtering.
3.3.2.35
0x004A
15
Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0
FMSK 0 0 0 0 0 0
Figure 3-34. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
This register defines the sync frame acceptance filter mask. For details on filtering see Section 3.4.15.1, "Sync Frame Acceptance Filtering".
Table 3-41. SFIDAFMR Field Descriptions
Field 9-0 FMSK Description Filter Mask -- This field defines the mask for the sync frame acceptance filtering.
3.3.2.36
15
Network Management Vector Registers (NMVR0-NMVR5)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x004C, 0x004E, 0x0050, 0x0052, 0x0054, 0x0056 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMVP[15:8] NMVP[7:0]
Figure 3-35. Network Management Vector Registers (NMVR0-NMVR5)
Each of these six registers holds one part of the Network Management Vector. The length of the Network Management Vector is configured in the Network Management Vector Length Register (NMVLR). If NMVLR is programmed with a value that is less than 12 bytes, the remaining bytes of the Network
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 101
FlexRay Module (FLEXRAYV2)
Management Vector Registers (NMVR0-NMVR5), which are not used for the Network Management Vector accumulating, will remain 0's. The NMVR provides accrued information over all received NMVs in the last communication cycle. All NMVs received in one cycle are ORed into the NMVR. The NMVR is updated at the end of the communication cycle.
Table 3-42. NMVR[0:5] Field Descriptions
Field 15-0 NMVP Description Network Management Vector Part -- The mapping between the Network Management Vector Registers (NMVR0-NMVR5) and the receive message buffer payload bytes in NMV[0:11] is depicted in Table 3-43.
Table 3-43. Mapping of NMVRn to the Received Payload Bytes NMVn
NMVRn Register NMVR0.NMVP[15:8] NMVR0.NMVP[7:0] NMVR1.NMVP[15:8] NMVR1.NMVP[7:0] ... NMVR5.NMVP[15:8] NMVR5.NMVP[7:0] NMV10 NMV11 NMVn Received Payload NMV0 NMV1 NMV2 NMV3
3.3.2.37
0x0058
15
Network Management Vector Length Register (NMVLR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0
NMVL 0 0 0
Figure 3-36. Network Management Vector Length Register (NMVLR)
This register defines the length of the network management vector in bytes.
Table 3-44. NMVLR Field Descriptions
Field 3-0 NMVL Description Network Management Vector Length -- protocol related variable: gNetworkManagementVectorLength This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12.
MFR4300 Data Sheet, Rev. 3 102 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.38
0x005A
15
Timer Configuration and Control Register (TICCR)
Write: T2_CFG: POC:config Write: T2_REP, T1_REP, T1SP, T2SP, T1TR, T2TR: Normal Mode
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T2_CFG
R W Reset
0
0
T2_REP
0
0
0
T2ST
0
0
0
T2SP T2TR 0 0 0 0 0 0 0
T1_ REP 0
0
0
0
T1ST
T1SP T1TR 0 0 0 0
0
0
0
0
Figure 3-37. Timer Configuration and Control Register (TICCR)
This register is used to configure and control the timers T1 and T2. For timer details, see Section 3.4.17, "Timer Support". Timer T1 is an absolute timer. Timer T2 can be configured as an absolute or relative timer.
Table 3-45. TICCR Field Descriptions
Field 13 T2_CFG 12 T2_REP 10 T2SP 9 T2TR 8 T2ST 4 T1_REP 2 T1SP 1 T1TR 0 T1ST Description Timer T2 Configuration -- This bit configures the timebase mode of Timer T2. 0 T2 is absolute timer. 1 T2 is relative timer. Timer T2 Repetitive Mode -- This bit configures the repetition mode of Timer T2. 0 T2 is non repetitive 1 T2 is repetitive Timer T2 Stop -- This trigger bit is used to stop timer T2. 0 no effect 1 stop timer T2 Timer T2 Trigger -- This trigger bit is used to start timer T2. 0 no effect 1 start timer T2 Timer T2 State -- This status bit provides the current state of timer T2. 0 timer T2 is idle 1 timer T2 is running Timer T1 Repetitive Mode -- This bit configures the repetition mode of timer T1. 0 T1 is non repetitive 1 T1 is repetitive Timer T1 Stop -- This trigger bit is used to stop timer T1. 0 no effect 1 stop timer T1 Timer T1 Trigger -- This trigger bit is used to start timer T1. 0 no effect 1 start timer T1 Timer T1 State -- This status bit provides the current state of timer T1. 0 timer T1 is idle 1 timer T1 is running
NOTE Both timers are deactivated immediately when the protocol enters a state different from POC:normal active or POC:normal passive.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 103
FlexRay Module (FLEXRAYV2)
3.3.2.39
0x005C
15
Timer 1 Cycle Set Register (TI1CYSR)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0 0 0
T1_CYC_VAL 0 0 0 0
0 0
0 0 0 0
T1_CYC_MSK 0 0 0 0
Figure 3-38. Timer 1 Cycle Set Register (TI1CYSR)
This register defines the cycle filter value and the cycle filter mask for timer T1. For a detailed description of timer T1, refer to Section 3.4.17.1, "Absolute Timer T1".
Table 3-46. TI1CYSR Field Descriptions
Field 13-8 T1_CYC_VAL Description Timer T1 Cycle Filter Value -- This field defines the cycle filter value for timer T1.
5-0 Timer T1 Cycle Filter Mask -- This field defines the cycle filter mask for timer T1. T1_CYC_MSK
NOTE If this register is modified while timer is running, the change becomes effective immediately.
3.3.2.40
0x005E
15
Timer 1 Macrotick Offset Register (TI1MTOR)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0 0 0 0 0 0 0
T1_MTOFFSET 0 0 0 0 0 0 0 0
Figure 3-39. Timer 1 Macrotick Offset Register (TI1MTOR)
This register holds the macrotick offset value for timer T1. For a detailed description of timer T1, refer to Section 3.4.17.1, "Absolute Timer T1".
Table 3-47. TI1MTOR Field Descriptions
Field Description
13-0 Timer 1 Macrotick Offset -- This field defines the macrotick offset value for timer 1. T1_MTOFFSET
NOTE If the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer T1 will expire according to the changed value.
MFR4300 Data Sheet, Rev. 3 104 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.41
0x0060
15
Timer 2 Configuration Register 0 (TI2CR0)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W R W Reset
0
0
T2_CYC_VAL
0
0
T2_CYC_MSK
T2_MTCNT[31:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-40. Timer 2 Configuration Register 0 (TI2CR0)
The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (TICCR). For a detailed description of timer T2, refer to Section 3.4.17.2, "Absolute / Relative Timer T2".
Table 3-48. TI2CR0 Field Descriptions
Field Description Fields for absolute timer T2 (TICCR.T2_CFG = `0') 13-8 T2_CYC_VAL 5-0 T2_CYC_MSK Timer T2 Cycle Filter Value -- This field defines the cycle filter value for timer T2. Timer T2 Cycle Filter Mask -- This field defines the cycle filter mask for timer T2. Fields for relative timer T2 (TICCR.T2_CFG = `1') 15-0 Timer T2 Macrotick High Word -- This field defines the high word of the macrotick count for timer T2. T2_MTCNT[31:16]
NOTE If timer T2 is configured as an absolute timer and the application modifies the values in this register while the timer is running, the change becomes effective immediately and timer T2 will expire according to the changed values. If timer T2 is configured as a relative timer and the application changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 105
FlexRay Module (FLEXRAYV2)
3.3.2.42
0x0062
15
Timer 2 Configuration Register 1 (TI2CR1)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W R W Reset
0
0
T2_MTOFFSET T2_MTCNT[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-41. Timer 2 Configuration Register 1 (TI2CR1)
The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (TICCR). For a detailed description of timer T2, refer to Section 3.4.17.2, "Absolute / Relative Timer T2".
Table 3-49. TI2CR1 Field Descriptions
Field Description Fields for absolute timer T2 (TICCR.T2_CFG = `0') 13-0 T2_MTOFFSET 15-0 T2_MTCNT[15:0] Timer T2 Macrotick Offset -- This field holds the macrotick offset value for timer T2. Fields for relative timer T2 (TICCR.T2_CFG = `1') Timer T2 Macrotick Low Word -- This field defines the low word of the macrotick value for timer T2.
NOTE If timer T2 is configured as an absolute timer and the application modifies the values in this register while the timer is running, the change becomes effective immediately and the timer T2 will expire according to the changed values. If timer T2 is configured as a relative timer and the application changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values.
3.3.2.43
0x0064
15
Slot Status Selection Register (SSSR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5 4 3 2
Write: Any Time
1 0
R Reset
0 0
0 0 0
W WMD
SEL 0
0 0 0 0 0 0
SLOTNUMBER 0 0 0 0 0 0 0
Figure 3-42. Slot Status Selection Register (SSSR)
This register is used to access the four internal non memory-mapped slot status selection registers SSSR0 to SSSR3. Each internal registers selects a slot, or symbol window/NIT, whose status vector will be saved
MFR4300 Data Sheet, Rev. 3 106 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
in the corresponding Slot Status Registers (SSR0-SSR7) according to Table 3-51. For a detailed description of slot status monitoring, refer to Section 3.4.18, "Slot Status Monitoring".
Table 3-50. SSSR Field Descriptions
Field 15 WMD 13-12 SEL Description Write Mode -- This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. Selector -- This field selects one of the four internal slot status selection registers for access. 00 select SSSR0. 01 select SSSR1. 10 select SSSR2. 11 select SSSR3.
10-0 Slot Number -- This field specifies the number of the slot whose status will be saved in the corresponding SLOTNUMBER slot status registers. Note: If this value is set to 0, the related slot status register provides the status of the symbol window after the NIT start, and provides the status of the NIT after the cycle start.
Table 3-51. Mapping Between SSSRn and SSRn
Write the Slot Status of the Slot Selected by SSSRn for each Internal Slot Status Selection Register SSSR0 SSSR1 SSSR2 SSSR3 Even Communication Cycle For Channel B to SSR0[15:8] SSR2[15:8] SSR4[15:8] SSR6[15:8] For Channel A to SSR0[7:0] SSR2[7:0] SSR4[7:0] SSR6[7:0] Odd Communication Cycle For Channel B to SSR1[15:8] SSR3[15:8] SSR5[15:8] SSR7[15:8] For Channel A to SSR1[7:0] SSR3[7:0] SSR5[7:0] SSR7[7:0]
3.3.2.44
0x0066
15
Slot Status Counter Condition Register (SSCCR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5 4 3 2
Write: Any Time
1 0
R Reset
0 0
0 0 0
W WMD
SEL 0
0 0
CNTCFG 0 0
MCY 0
VFR 0
SYF 0
NUF 0
SUF 0 0
STATUSMASK 0 0 0
Figure 3-43. Slot Status Counter Condition Register (SSCCR)
This register is used to access and program the four internal non-memory mapped Slot Status Counter Condition Registers SSCCR0 to SSCCR3. Each of these four internal slot status counter condition registers defines the mode and the conditions for incrementing the counter in the corresponding Slot Status Counter Registers (SSCR0-SSCR3). The correspondence is given in Table 3-53. For a detailed description of slot status counters, refer to Section 3.4.18.4, "Slot Status Counter Registers".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 107
FlexRay Module (FLEXRAYV2)
Table 3-52. SSCCR Field Descriptions
Field 15 WMD 13-12 SEL Description Write Mode -- This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. Selector -- This field selects one of the four internal slot counter condition registers for access. 00 select SSCCR0. 01 select SSCCR1. 10 select SSCCR2. 11 select SSCCR3. Counter Configuration -- These bit field controls the channel related incrementing of the slot status counter. 00 increment by 1 if condition is fulfilled on channel A. 01 increment by 1 if condition is fulfilled on channel B. 10 increment by 1 if condition is fulfilled on at least one channel. 11 increment by 2 if condition is fulfilled on both channels channel. increment by 1 if condition is fulfilled on only one channel. Multi Cycle Selection -- This bit defines whether the slot status counter accumulates over multiple communication cycles or provides information for the previous communication cycle only. 0 The Slot Status Counter provides information for the previous communication cycle only. 1 The Slot Status Counter accumulates over multiple communication cycles. Valid Frame Restriction -- This bit is used to restrict the counter to received valid frames. 0 The counter is not restricted to valid frames only. 1 The counter is restricted to valid frames only. Sync Frame Restriction -- This bit is used to restrict the counter to received frames with the sync frame indicator bit set to `1'. 0 The counter is not restricted with respect to the sync frame indicator bit. 1 The counter is restricted to frames with the sync frame indicator bit set to `1'. Null Frame Restriction -- This bit is used to restrict the counter to received frames with the null frame indicator bit set to `0'. 0 The counter is not restricted with respect to the null frame indicator bit. 1 The counter is restricted to frames with the null frame indicator bit set to `0'. Startup Frame Restriction -- This bit is used to restrict the counter to received frames with the startup frame indicator bit set to `1'. 0 The counter is not restricted with respect to the startup frame indicator bit. 1 The counter is restricted to received frames with the startup frame indicator bit set to `1'.
10-9 CNTCFG
8 MCY
7 VFR 6 SYF
5 NUF
4 SUF
3-0 Slot Status Mask -- This bit field is used to enable the counter with respect to the four slot status error STATUSMASK indicator bits. STATUSMASK[3] - This bit enables the counting for slots with the syntax error indicator bit set to `1'. STATUSMASK[2] - This bit enables the counting for slots with the content error indicator bit set to `1'. STATUSMASK[1] - This bit enables the counting for slots with the boundary violation indicator bit set to `1'. STATUSMASK[0] - This bit enables the counting for slots with the transmission conflict indicator bit set to `1'.
Table 3-53. Mapping between internal SSCCRn and SSCRn
Condition Register SSCCR0 SSCCR1 SSCCR2 SSCCR3 Condition Defined for Register SSCR0 SSCR1 SSCR2 SSCR3
MFR4300 Data Sheet, Rev. 3 108 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.45
15
Slot Status Registers (SSR0-SSR7)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0068, 0x006A, 0x006C, 0x006E, 0x0070, 0x0072, 0x0074, 0x0076 R VFB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYB NFB SUB SEB CEB BVB TCB VFA SYA NFA SUA SEA CEA BVA TCA
Figure 3-44. Slot Status Registers (SSR0-SSR7)
Each of these eight registers holds the status vector of the slot specified in the corresponding internal slot status selection register, which can be programmed using the Slot Status Selection Register (SSSR). Each register is updated after the end of the corresponding slot as shown in Figure 3-139. The register bits are directly related to the protocol variables and described in more detail in Section 3.4.18, "Slot Status Monitoring".
Table 3-54. SSR0-SSR7 Field Descriptions
Field 15 VFB 14 SYB 13 NFB 12 SUB 11 SEB 10 CEB 9 BVB 8 TCB 7 VFA 6 SYA Description Valid Frame on Channel B -- protocol related variable: vSS!ValidFrame channel B 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel B -- protocol related variable: vRF!Header!SyFIndicator channel B 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1' Null Frame Indicator Channel B -- protocol related variable: vRF!Header!NFIndicator channel B 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel B -- protocol related variable: vRF!Header!SuFIndicator channel B 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1' Syntax Error on Channel B -- protocol related variable: vSS!SyntaxError channel B 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel B -- protocol related variable: vSS!ContentError channel B 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' Boundary Violation on Channel B -- protocol related variable: vSS!BViolation channel B 0 vSS!BViolation = `0' 1 vSS!BViolation = `1' Transmission Conflict on Channel B -- protocol related variable: vSS!TxConflict channel B 0 vSS!TxConflict = `0' 1 vSS!TxConflict = `1' Valid Frame on Channel A -- protocol related variable: vSS!ValidFrame channel A 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel A -- protocol related variable: vRF!Header!SyFIndicator channel A 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1'
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 109
FlexRay Module (FLEXRAYV2)
Table 3-54. SSR0-SSR7 Field Descriptions (Continued)
Field 5 NFA 4 SUA 3 SEA 2 CEA 1 BVA 0 TCA Description Null Frame Indicator Channel A -- protocol related variable: vRF!Header!NFIndicator channel A 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel A -- protocol related variable: vRF!Header!SuFIndicator channel A 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1' Syntax Error on Channel A -- protocol related variable: vSS!SyntaxError channel A 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel A -- protocol related variable: vSS!ContentError channel A 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' Boundary Violation on Channel A -- protocol related variable: vSS!BViolation channel A 0 vSS!BViolation = `0' 1 vSS!BViolation = `1' Transmission Conflict on Channel A -- protocol related variable: vSS!TxConflict channel A 0 vSS!TxConflict = `0' 1 vSS!TxConflict = `1'
3.3.2.46
15
Slot Status Counter Registers (SSCR0-SSCR3)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0078, 0x007A, 0x007C, 0x007E R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOTSTATUSCNT
Figure 3-45. Slow Status Counter Registers (SSCR0-SSCR3)
Additional Reset: [RUN Command] Each of these four registers provides the slot status counter value for the previous communication cycle(s) and is updated at each cycle start. The value depends on the control bits and fields in the related internal slot status counter condition register, which can be programmed by using the Slot Status Counter Condition Register (SSCCR). For more details, see Section 3.4.18.4, "Slot Status Counter Registers". NOTE If the counter has reached its maximum value 0xFFFF and is in the multicycle mode, i.e. SSCCRx.MCY = `1', the counter is not reset to 0x0000. The application can reset the counter by clearing the MCY bit and waiting for the next cycle start, when the FlexRay module clears the counter. Subsequently, the counter can be set into the multicycle mode again.
MFR4300 Data Sheet, Rev. 3 110 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-55. SSCR0-SSCR3 Field Descriptions
Field Description
15-0 Slot Status Counter -- This field provides the current value of the Slot Status Counter. SLOTSTATUSCNT
3.3.2.47
0x0080
15
MTS A Configuration Register (MTSACFR)
Write: CYCCNTMSK, CYCCNTVAL: POC:config Write: MTE: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
MTE 0
0 0 0 0
CYCCNTMSK 0 0 0 0
0 0
0 0 0 0
CYCCNTVAL 0 0 0 0
Figure 3-46. MTS A Configuration Register (MTSACFR)
This register controls the transmission of the Media Access Test Symbol MTS on channel A. For more details, see Section 3.4.13, "MTS Generation".
Table 3-56. MTSACFR Field Descriptions
Field 15 MTE Description Media Access Test Symbol Transmission Enable -- This control bit is used to enable and disable the transmission of the Media Access Test Symbol in the selected set of cycles. 0 MTS transmission disabled 1 MTS transmission enabled
13-8 Cycle Counter Mask -- This field provides the filter mask for the MTS cycle count filter. CYCCNTMSK 5-0 Cycle Counter Value -- This field provides the filter value for the MTS cycle count filter. CYCCNTVAL
3.3.2.48
0x0082
15
MTS B Configuration Register (MTSBCFR)
Write: CYCCNTMSK, CYCCNTVAL: POC:config Write: MTE: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
MTE 0
0 0 0 0
CYCCNTMSK 0 0 0 0
0 0
0 0 0 0
CYCCNTVAL 0 0 0 0
Figure 3-47. MTS B Configuration Register (MTSBCFR)
This register controls the transmission of the Media Access Test Symbol MTS on channel B. For more details, see Section 3.4.13, "MTS Generation".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 111
FlexRay Module (FLEXRAYV2)
Table 3-57. MTSBCFR Field Descriptions
Field 15 MTE Description Media Access Test Symbol Transmission Enable -- This control bit is used to enable and disable the transmission of the Media Access Test Symbol in the selected set of cycles. 0 MTS transmission disabled 1 MTS transmission enabled
13-8 Cycle Counter Mask -- This field provides the filter mask for the MTS cycle count filter. CYCCNTMSK 5-0 Cycle Counter Value -- This field provides the filter value for the MTS cycle count filter. CYCCNTVAL
3.3.2.49
0x0084
15
Receive Shadow Buffer Index Register (RSBIR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5 4
Write: WMD, SEL: Any Time Write: RSBIDX: POC:config
3 2 1 0
R Reset
0 0
0 0 0
W WMD
SEL 0
0 0
0 0
0 0
0 0 0 0 0
RSBIDX 0 0 0 0 0
Figure 3-48. Receive Shadow Buffer Index Register (RSBIR)
This register is used to provide and retrieve the indices of the message buffer header fields currently associated with the receive shadow buffers. For more details on the receive shadow buffer concept, refer to Section 3.4.6.3.6, "Receive Shadow Buffers Concept".
Table 3-58. RSBIR Field Descriptions
Field 15 WMD 13-12 SEL Description Write Mode -- This bit controls the write mode for this register. 0 update SEL and RSBIDX field on register write 1 update only SEL field on register write Selector -- This field is used to select the internal receive shadow buffer index register for access. 00 RSBIR_A1 -- receive shadow buffer index register for channel A, segment 1 01 RSBIR_A2 -- receive shadow buffer index register for channel A, segment 2 10 RSBIR_B1 -- receive shadow buffer index register for channel B, segment 1 11 RSBIR_B2 -- receive shadow buffer index register for channel B, segment 2 Receive Shadow Buffer Index -- This field contains the current index of the message buffer header field of the receive shadow message buffer selected by the SEL field. The FlexRay module uses this index to determine the physical location of the shadow buffer header field in the FlexRay memory. The FlexRay module will update this field during receive operation.The application provides initial message buffer header index value in the configuration phase. FlexRay module: Updates the message buffer header index after successful reception. Application: Provides initial message buffer header index.
7-0 RSBIDX
MFR4300 Data Sheet, Rev. 3 112 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.50
0x0086
15
Receive FIFO Selection Register (RFSR)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
SEL 0
Figure 3-49. Receive FIFO Selection Register (RFSR)
This register is used to select a receiver FIFO for subsequent access through the receiver FIFO configuration registers summarized in Table 3-59.
Table 3-59. SEL Controlled Receiver FIFO Registers
Register Receive FIFO Start Index Register (RFSIR) Receive FIFO Depth and Size Register (RFDSR) Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) Receive FIFO Range Filter Configuration Register (RFRFCFR) Receive FIFO Range Filter Control Register (RFRFCTR)
Table 3-60. RFSR Field Descriptions
Field 0 SEL Description Select -- This control bit selects the receiver FIFO for subsequent programming. 0 Receiver FIFO for channel A selected 1 Receiver FIFO for channel B selected
3.3.2.51
0x0088
15
Receive FIFO Start Index Register (RFSIR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0
SIDX 0 0 0 0
Figure 3-50. Receive FIFO Start Index Register (RFSIR)
This register defines the message buffer header index of the first message buffer that belongs to the selected receive FIFO.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 113
FlexRay Module (FLEXRAYV2)
Table 3-61. RFSIR Field Descriptions
Field 7-0 SIDX Description Start Index -- This field defines the number of the message buffer header field of the first message buffer of the selected receive FIFO. The FlexRay module uses the value of the SIDX field to determine the physical location of the receiver FIFO's first message buffer header field.
3.3.2.52
0x008A
15
Receive FIFO Depth and Size Register (RFDSR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0
FIFO_DEPTH 0 0 0 0 0
0 0 0 0
ENTRY_SIZE 0 0 0 0 0
Figure 3-51. Receive FIFO Depth and Size Register (RFDSR)
This register defines the structure of the selected receive FIFO, i.e. the number of entries and the size of each entry.
Table 3-62. RFDSR Field Descriptions
Field Description
15-8 FIFO Depth -- This field defines the depth of the selected receive FIFO, i.e. the number of entries. FIFO_DEPTH 6-0 Entry Size -- This field defines the size of the frame data sections for the selected receive FIFO in 2 byte ENTRY_SIZE entities.
3.3.2.53
0x008C
15
Receive FIFO A Read Index Register (RFARIR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
RDIDX 0 0 0 0 0
Figure 3-52. Receive FIFO A Read Index Register (RFARIR)
This register provides the message buffer header index of the next available entry of receive FIFO A that the application can read.
Table 3-63. RFARIR Field Descriptions
Field 7-0 RDIDX Description Read Index -- This field provides the message buffer header index of the next available receive FIFO message buffer that the application can read. The FlexRay module increments this index when the application writes to the FNEAIF flag in the Global Interrupt Flag and Enable Register (GIFER). The index wraps back to the first message buffer header index if the end of the FIFO was reached.
MFR4300 Data Sheet, Rev. 3 114 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
NOTE If the receive FIFO not empty flag FNEAIF is not set, the RDIDX fields points to an physical message buffers that is invalid. Only when FNEAIF is set, the message buffer indicated by RDIDX contains valid data.
3.3.2.54
0x008E
15
Receive FIFO B Read Index Register (RFBRIR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
RDIDX 0 0 0 0 0
Figure 3-53. Receive FIFO B Read Index Register (RFBRIR)
This register provides the message buffer header index of the next available entry of receive FIFO A that the application can read.
Table 3-64. RFBRIR Field Descriptions
Field 7-0 RDIDX Description Read Index -- This field provides the message buffer header index of the next available receive FIFO entry that the application can read. The FlexRay module increments this index when the application writes to the FNEBIF flag in the Global Interrupt Flag and Enable Register (GIFER).The index wraps back to the first message buffer header index if the end of the FIFO was reached.
NOTE If the receive FIFO not empty flag FNEBIF is not set, the RDIDX fields points to an physical message buffers that is invalid. Only when FNEBIF is set, the message buffer indicated by RDIDX contains valid data.
3.3.2.55
0x0090
15
Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
MIDAFVAL 0 0 0 0 0 0 0 0 0
Figure 3-54. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
This register defines the filter value for the message ID acceptance filter of the selected receive FIFO. For details on message ID filtering see Section 3.4.9.5, "Receive FIFO filtering".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 115
FlexRay Module (FLEXRAYV2)
Table 3-65. RFMIDAFVR Field Descriptions
Field 15-0 MIDAFVAL Description Message ID Acceptance Filter Value -- Filter value for the message ID acceptance filter.
3.3.2.56
0x0092
15
Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
MIDAFMSK 0 0 0 0 0 0 0 0 0
Figure 3-55. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
This register defines the filter mask for the message ID acceptance filter of the selected receive FIFO. For details on message ID filtering see Section 3.4.9.5, "Receive FIFO filtering".
Table 3-66. RFMIAFMR Field Descriptions
Field 15-0 MIDAFMSK Description Message ID Acceptance Filter Mask -- Filter mask for the message ID acceptance filter.
3.3.2.57
0x0094
15
Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0
FIDRFVAL 0 0 0 0 0 0
Figure 3-56. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
This register defines the filter value for the frame ID rejection filter of the selected receive FIFO. For details on frame ID filtering see Section 3.4.9.5, "Receive FIFO filtering".
Table 3-67. RFFIDRFVR Field Descriptions
Field 10-0 FIDRFVAL Description Frame ID Rejection Filter Value -- Filter value for the frame ID rejection filter.
MFR4300 Data Sheet, Rev. 3 116 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.58
0x0096
15
Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0
FIDRFMSK 0 0 0 0 0 0
Figure 3-57. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
This register defines the filter mask for the frame ID rejection filter of the selected receive FIFO. For details on frame ID filtering see Section 3.4.9.5, "Receive FIFO filtering".
Table 3-68. RFFIDRFMR Field Descriptions
Field 10-0 FIDRFMSK Description Frame ID Rejection Filter Mask -- Filter mask for the frame ID rejection filter.
3.3.2.59
0x0098
15
Receive FIFO Range Filter Configuration Register (RFRFCFR)
16-bit write access required
14 13 12 11 10 9 8 7 6 5
Write: WMD, IBD, SEL: Any Time Write: SID: POC:config
4 3 2 1 0
R Reset
0 0
W WMD
IBD 0 0
SEL 0
0 0 0 0 0 0 0
SID 0 0 0 0 0 0
Figure 3-58. Receive FIFO Range Filter Configuration Register (RFRFCFR)
This register provides access to the four internal frame ID range filter boundary registers of the selected receive FIFO. For details on frame ID range filter see Section 3.4.9.5, "Receive FIFO filtering".
Table 3-69. RFRFCFR Field Descriptions
Field 15 WMD 14 IBD 13-12 SEL Description Write Mode -- This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL and IBD field only on write access. Interval Boundary -- This control bit selects the interval boundary to be programmed with the SID value. 0 program lower interval boundary 1 program upper interval boundary Filter Selector -- This control field selects the frame ID range filter to be accessed. 00 select frame ID range filter 0. 01 select frame ID range filter 1. 10 select frame ID range filter 2. 11 select frame ID range filter 3. Slot ID -- Defines the IBD-selected frame ID boundary value for the SEL-selected range filter.
10-0 SID
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 117
FlexRay Module (FLEXRAYV2)
3.3.2.60
0x009A
15
Receive FIFO Range Filter Control Register (RFRFCTR)
Write: Any Time
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
F3MD F2MD F1MD F0MD 0 0 0 0
0 0
0 0
0 0
0 0
F3EN F2EN F1EN F0EN 0 0 0 0
Figure 3-59. Receive FIFO Range Filter Control Register (RFRFCTR)
This register is used to enable and disable each frame ID range filter and to define whether it is running as acceptance or rejection filter.
Table 3-70. RFRFCTR Field Descriptions
Field 11 F3MD 10 F2MD 9 F1MD 8 F0MD 3 F3EN 2 F2EN 1 F1EN 0 F0EN Description Range Filter 3 Mode -- This control bit defines the filter mode of the frame ID range filter 3. 0 range filter 3 runs as acceptance filter 1 range filter 3 runs as rejection filter Range Filter 2 Mode -- This control bit defines the filter mode of the frame ID range filter 2. 0 range filter 2 runs as acceptance filter 1 range filter 2 runs as rejection filter Range Filter 1 Mode -- This control bit defines the filter mode of the frame ID range filter 1. 0 range filter 1 runs as acceptance filter 1 range filter 1 runs as rejection filter Range Filter 0 Mode -- This control bit defines the filter mode of the frame ID range filter 0. 0 range filter 0 runs as acceptance filter 1 range filter 0 runs as rejection filter Range Filter 3 Enable -- This control bit is used to enable and disable the frame ID range filter 3. 0 range filter 3 disabled 1 range filter 3 enabled Range Filter 2 Enable -- This control bit is used to enable and disable the frame ID range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled Range Filter 1 Enable -- This control bit is used to enable and disable the frame ID range filter 1. 0 range filter 1 disabled 1 range filter 1 enabled Range Filter 0 Enable -- This control bit is used to enable and disable the frame ID range filter 0. 0 range filter 0 disabled 1 range filter 0 enabled
3.3.2.61
0x009C
15
Last Dynamic Transmit Slot Channel A Register (LDTXSLAR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0
LASTDYNTXSLOTA 0 0 0 0 0 0 0
Figure 3-60. Last Dynamic Slot Channel A Register (LDTXSLAR)
MFR4300 Data Sheet, Rev. 3 118 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
This register provides the number of the last transmission slot in the dynamic segment for channel A. This register is updated after the end of the dynamic segment and before the start of the next communication cycle.
Table 3-71. LDTXSLAR Field Descriptions
Field Description
10-0 Last Dynamic Transmission Slot Channel A -- protocol related variable: zLastDynTxSlot channel A LASTDYNTX Number of the last transmission slot in the dynamic segment for channel A. If no frame was transmitted during SLOTA the dynamic segment on channel A, the value of this field is set to 0.
3.3.2.62
0x009E
15
Last Dynamic Transmit Slot Channel B Register (LDTXSLBR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0 0 0 0
LASTDYNTXSLOTB 0 0 0 0 0 0 0
Figure 3-61. Last Dynamic Slot Channel B Register (LDTXSLBR)
This register provides the number of the last transmission slot in the dynamic segment for channel B. This register is updated after the end of the dynamic segment and before the start of the next communication cycle.
Table 3-72. LDTXSLBR Field Descriptions
Field Description
10-0 Last Dynamic Transmission Slot Channel B -- protocol related variable: zLastDynTxSlot channel B LASTDYNTX Number of the last transmission slot in the dynamic segment for channel B. If no frame was transmitted during SLOTB the dynamic segment on channel B the value of this field is set to 0.
3.3.2.63
Protocol Configuration Registers
The following configuration registers provide the necessary configuration information to the protocol engine. The individual values in the registers are described in Table 3-73. For more details about the FlexRay related configuration parameters and the allowed parameter ranges, see FlexRay Communications System Protocol Specification, Version 2.1.
Table 3-73. Protocol Configuration Register Fields (Sheet 1 of 3)
Name coldstart_attempts action_point_offset cas_rx_low_max dynamic_slot_idle_phase minislot_action_point_offset minislot_after_action_point static_slot_length Description1 gColdstartAttempts gdActionPointOffset - 1 gdCASRxLowMax - 1 gdDynamicSlotIdlePhase gdMinislotActionPointOffset - 1 gdMinislot - gdMinislotActionPointOffset - 1 gdStaticSlot Min Max Unit number MT gdBit minislot MT MT MT PCR 3 0 4 28 3 2 0
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 119
FlexRay Module (FLEXRAYV2)
Table 3-73. Protocol Configuration Register Fields (Sheet 2 of 3)
Name static_slot_after_action_point symbol_window_exists symbol_window_after_action_point tss_transmitter wakeup_symbol_rx_idle wakeup_symbol_rx_low wakeup_symbol_rx_window wakeup_symbol_tx_idle wakeup_symbol_tx_low noise_listen_timeout macro_initial_offset_a macro_initial_offset_b macro_per_cycle macro_after_first_static_slot macro_after_offset_correction max_without_clock_correction_fatal minislot_exists minislots_max number_of_static_slots offset_correction_start payload_length_static max_payload_length_dynamic first_minislot_action_point_offset allow_halt_due_to_clock allow_passive_to_active cluster_drift_damping comp_accepted_startup_range_a comp_accepted_startup_range_b listen_timeout key_slot_id key_slot_used_for_startup key_slot_used_for_sync latest_tx sync_node_max micro_initial_offset_a micro_initial_offset_b Description1 gdStaticSlot - gdActionPointOffset - 1 gdSymbolWindow!=0 gdSymbolWindow - gdActionPointOffset - 1 gdTSSTransmitter gdWakeupSymbolRxIdle gdWakeupSymbolRxLow gdWakeupSymbolRxWindow gdWakeupSymbolTxIdle gdWakeupSymbolTxLow (gListenNoise * pdListenTimeout) - 1 pMacroInitialOffset[A] pMacroInitialOffset[B] gMacroPerCycle gMacroPerCycle - gdStaticSlot gMacroPerCycle - gOffsetCorrectionStart gMaxWithoutClockCorrectionFatal gNumberOfMinislots!=0 gNumberOfMinislots - 1 gNumberOfStaticSlots gOffsetCorrectionStart gPayloadLengthStatic pPayloadLengthDynMax max(gdActionPointOffset, gdMinislotActionPointOffset) - 1 pAllowHaltDueToClock pAllowPassiveToActive pClusterDriftDamping pdAcceptedStartupRange pDelayCompensationChA pdAcceptedStartupRange pDelayCompensationChB pdListenTimeout - 1 pKeySlotId pKeySlotUsedForStartup pKeySlotUsedForSync gNumberOfMinislots - pLatestTx gSyncNodeMax pMicroInitialOffset[A] pMicroInitialOffset[B] 0 1 0 1 Min Max Unit MT bool MT gdBit gdBit gdBit gdBit gdBit gdBit T MT MT MT MT MT cyclepairs cyclepairs bool minislot static slot MT 2-bytes 2-bytes MT bool cyclepairs T T T T number bool bool minislot number T T PCR 13 9 6 5 5 3 4 8 5 16/17 6 16 10 1 28 8 8 9 29 2 11 19 24 13 26 12 24 22 26 14/15 18 11 11 21 30 20 20
max_without_clock_correction_passive gMaxWithoutClockCorrectionPassive
MFR4300 Data Sheet, Rev. 3 120 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-73. Protocol Configuration Register Fields (Sheet 3 of 3)
Name micro_per_cycle micro_per_cycle_min micro_per_cycle_max micro_per_macro_nom_half offset_correction_out rate_correction_out single_slot_enabled wakeup_channel wakeup_pattern decoding_correction_a decoding_correction_b key_slot_header_crc extern_offset_correction extern_rate_correction
1
Description1 pMicroPerCycle pMicroPerCycle - pdMaxDrift pMicroPerCycle + pdMaxDrift round(pMicroPerMacroNom / 2) pOffsetCorrectionOut pRateCorrectionOut pSingleSlotEnabled pWakeupChannel pWakeupPattern pDecodingCorrection + pDelayCompensation[A] + 2 pDecodingCorrection + pDelayCompensation[B] + 2 header CRC for key slot pExternOffsetCorrection pExternRateCorrection
Min
Max
Unit T T T T T T bool
PCR 22/23 24/25 26/27 7 9 14 10 10 18 19 7 12 29 21
see Table 3-74 number T T 0x000 0x7FF number T T
See FlexRay Communications System Protocol Specification, Version 2.1 for detailed protocol parameter definitions
Table 3-74. Wakeup Channel Selection
wakeup_channel 0 1 Wakeup Channel A B
3.3.2.63.1
0x00A0
15
Protocol Configuration Register 0 (PCR0)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0
action_point_offset 0 0 0 0 0 0 0 0
static_slot_length 0 0 0 0 0 0
Figure 3-62. Protocol Configuration Register 0 (PCR0)
3.3.2.63.2
0x00A2
15
Protocol Configuration Register 1 (PCR1)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0 0 0 0 0 0
macro_after_first_static_slot 0 0 0 0 0 0 0 0 0
Figure 3-63. Protocol Configuration Register 1 (PCR1)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 121
FlexRay Module (FLEXRAYV2)
3.3.2.63.3
0x00A4
15
Protocol Configuration Register 2 (PCR2)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0
minislot_after_action_point 0 0 0 0 0 0 0 0
number_of_static_slots 0 0 0 0 0 0 0
Figure 3-64. Protocol Configuration Register 2 (PCR2)
3.3.2.63.4
0x00A6
15
Protocol Configuration Register 3 (PCR3)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0
wakeup_symbol_rx_low 0 0 0 0 0
minislot_action_point_offset[4:0] 0 0 0 0 0 0
coldstart_attempts 0 0 0 0
Figure 3-65. Protocol Configuration Register 3 (PCR3)
3.3.2.63.5
0x00A8
15
Protocol Configuration Register 4 (PCR4)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0
cas_rx_low_max 0 0 0 0 0 0 0 0
wakeup_symbol_rx_window 0 0 0 0 0 0
Figure 3-66. Protocol Configuration Register 4 (PCR4)
3.3.2.63.6
0x00AA
15
Protocol Configuration Register 5 (PCR5)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0
tss_transmitter 0 0 0 0
wakeup_symbol_tx_low 0 0 0 0 0 0
wakeup_symbol_rx_idle 0 0 0 0 0
Figure 3-67. Protocol Configuration Register 5 (PCR5)
3.3.2.63.7
0x00AC
15
Protocol Configuration Register 6 (PCR6)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0 0 0
symbol_window_after_action_point 0 0 0 0 0 0 0 0
macro_initial_offset_a 0 0 0 0 0
Figure 3-68. Protocol Configuration Register 6 (PCR6)
MFR4300 Data Sheet, Rev. 3 122 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.63.8
0x00AE
15
Protocol Configuration Register 7 (PCR7)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0
decoding_correction_b 0 0 0 0 0 0 0 0
micro_per_macro_nom_half 0 0 0 0 0
Figure 3-69. Protocol Configuration Register 7 (PCR7)
3.3.2.63.9
0x00B0
15
Protocol Configuration Register 8 (PCR8)
Write: POC:config
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0
max_without_clock_ correction_fatal 0 0 0 0
max_without_clock_ correction_passive 0 0 0 0 0
wakeup_symbol_tx_idle 0 0 0 0 0 0
Figure 3-70. Protocol Configuration Register 8 (PCR8)
3.3.2.63.10 Protocol Configuration Register 9 (PCR9)
0x00B2
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
sym mini bol_ slot_ win W exists dow_ exists Reset 0 0 0 0 0 0 0 0
R
offset_correction_out
0
0
0
0
0
0
0
0
Figure 3-71. Protocol Configuration Register 9 (PCR9)
3.3.2.63.11 Protocol Configuration Register 10 (PCR10)
0x00B4
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R single wake _slot up_ W _en chan abled nel Reset 0 0 0 0 0 0 0 0
macro_per_cycle 0 0 0 0 0 0 0 0
Figure 3-72. Protocol Configuration Register 10 (PCR10)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 123
FlexRay Module (FLEXRAYV2)
3.3.2.63.12 Protocol Configuration Register 11 (PCR11)
0x00B6
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R key_ slot_ used_ W for_ start up Reset 0
key_ slot_ used_ for_ sync 0 0 0 0 0 0
offset_correction_start
0
0
0
0
0
0
0
0
0
Figure 3-73. Protocol Configuration Register 11 (PCR11)
3.3.2.63.13 Protocol Configuration Register 12 (PCR12)
0x00B8
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0
allow_passive_to_active 0 0 0 0 0 0 0 0
key_slot_header_crc 0 0 0 0 0 0 0
Figure 3-74. Protocol Configuration Register 12 (PCR12)
3.3.2.63.14 Protocol Configuration Register 13 (PCR13)
0x00BA
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0
first_minislot_action_point_offset 0 0 0 0 0 0 0 0
static_slot_after_action_point 0 0 0 0 0 0 0
Figure 3-75. Protocol Configuration Register 13 (PCR13)
3.3.2.63.15 Protocol Configuration Register 14 (PCR14)
0x00BC
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0
rate_correction_out 0 0 0 0 0 0 0 0
listen_timeout[20:16] 0 0 0 0
Figure 3-76. Protocol Configuration Register 14 (PCR14)
MFR4300 Data Sheet, Rev. 3 124 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.63.16 Protocol Configuration Register 15 (PCR15)
0x00BE
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0 0 0 0
listen_timeout[15:0] 0 0 0 0 0 0 0 0 0
Figure 3-77. Protocol Configuration Register 15 (PCR15)
3.3.2.63.17 Protocol Configuration Register 16 (PCR16)
0x00C0
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0
macro_initial_offset_b 0 0 0 0 0 0 0 0
noise_listen_timeout[24:16] 0 0 0 0 0 0
Figure 3-78. Protocol Configuration Register 16 (PCR16)
3.3.2.63.18 Protocol Configuration Register 17 (PCR17)
0x00C2
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0 0 0
noise_listen_timeout[15:0] 0 0 0 0 0 0 0 0 0 0
Figure 3-79. Protocol Configuration Register 17 (PCR17)
3.3.2.63.19 Protocol Configuration Register 18 (PCR18)
0x00C4
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0
wakeup_pattern 0 0 0 0 0 0 0 0
key_slot_id 0 0 0 0 0 0
Figure 3-80. Protocol Configuration Register 18 (PCR18)
3.3.2.63.20 Protocol Configuration Register 19 (PCR19)
0x00C6
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0
decoding_correction_a 0 0 0 0 0 0 0 0
payload_length_static 0 0 0 0 0
Figure 3-81. Protocol Configuration Register 19 (PCR19)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 125
FlexRay Module (FLEXRAYV2)
3.3.2.63.21 Protocol Configuration Register 20 (PCR20)
0x00C8
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0
micro_initial_offset_b 0 0 0 0 0 0 0 0
micro_initial_offset_a 0 0 0 0 0 0
Figure 3-82. Protocol Configuration Register 20 (PCR20)
3.3.2.63.22 Protocol Configuration Register 21 (PCR21)
0x00CA
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0
extern_rate_ correction 0 0 0 0 0 0 0 0
latest_tx 0 0 0 0 0 0 0
Figure 3-83. Protocol Configuration Register 21 (PCR21)
3.3.2.63.23 Protocol Configuration Register 22 (PCR22)
0x00CC
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset
R* 0 0 0 0
comp_accepted_startup_range_a 0 0 0 0 0 0 0 0
micro_per_cycle[19:16 0 0 0 0
Figure 3-84. Protocol Configuration Register 22 (PCR22)
3.3.2.63.24 Protocol Configuration Register 23 (PCR23)
0x00CE
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0 0 0
micro_per_cycle[15:0] 0 0 0 0 0 0 0 0 0 0
Figure 3-85. Protocol Configuration Register 23 (PCR23)
3.3.2.63.25 Protocol Configuration Register 24 (PCR24)
0x00D0
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0
cluster_drift_damping 0 0 0 0 0
max_payload_length_dynamic 0 0 0 0 0 0
micro_per_cycle_min [19:16] 0 0 0 0
Figure 3-86. Protocol Configuration Register 24 (PCR24)
MFR4300 Data Sheet, Rev. 3 126 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.3.2.63.26 Protocol Configuration Register 25 (PCR25)
0x00D2
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0 0 0
micro_per_cycle_min[15:0] 0 0 0 0 0 0 0 0 0 0
Figure 3-87. Protocol Configuration Register 25 (PCR25)
3.3.2.63.27 Protocol Configuration Register 26 (PCR26)
0x00D4
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R allow _halt_ W due _to_ clock Reset 0 0 0 0
comp_accepted_startup_range_b
micro_per_cycle_max [19:16] 0 0 0 0 0 0 0
0
0
0
0
0
Figure 3-88. Protocol Configuration Register 26 (PCR26)
3.3.2.63.28 Protocol Configuration Register 27 (PCR27)
0x00D6
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset 0 0 0 0 0 0
micro_per_cycle_max[15:0] 0 0 0 0 0 0 0 0 0 0
Figure 3-89. Protocol Configuration Register 27 (PCR27)
3.3.2.63.29 Protocol Configuration Register 28 (PCR28)
0x00D8
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R dynamic_slot W _idle_phase Reset 0 0 0 0 0 0 0
macro_after_offset_correction 0 0 0 0 0 0 0 0 0
Figure 3-90. Protocol Configuration Register 28 (PCR28)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 127
FlexRay Module (FLEXRAYV2)
3.3.2.63.30 Protocol Configuration Register 29 (PCR29)
0x00DA
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset
extern_offset_ correction 0 0 0 0 0 0 0 0
minislots_max 0 0 0 0 0 0 0 0
Figure 3-91. Protocol Configuration Register 29 (PCR29)
3.3.2.63.31 Protocol Configuration Register 30 (PCR30)
0x00DC
15 14 13 12 11 10 9 8 7 6 5 4 3
Write: POC:config
2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0
sync_node_max 0 0 0
Figure 3-92. Protocol Configuration Register 30 (PCR30)
3.3.2.64
Message Buffer Configuration, Control, Status Registers (MBCCSRn)
Write: MCM, MBT, MTD: POC:config or MB_DIS Write: CMT: MB_LCK Write: EDT, LCKT, MBIE, MBIF: Normal Mode
Module Base + 0x0100, 0x0108,..., 0x04F8
Additional Reset: CMT, DUP, DVAL, MBIF: Message Buffer Disable
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
MCM 0
MBT 0
MTD 0
CMT 0
0 EDT 0
0 LCKT 0
MBIE 0
0 0
0 0
0 0
DUP 0
DVAL 0
EDS LCKS 0 0
MBIF 0
Figure 3-93. Message Buffer Configuration, Control, Status Registers (MBCCSRn)
The content of these registers comprises message buffer configuration data, message buffer control data, message buffer status information, and message buffer interrupt flags.
Table 3-75. MBCCSRn Field Descriptions (Sheet 1 of 3)
Field Description Message Buffer Configuration 14 MCM Message Buffer Commit Mode -- This bit applies only to double buffered transmit message buffers and defines the commit mode. 0 Streaming commit mode 1 Immediate commit mode Message Buffer Type -- This bit applies only to transmit message buffers and defines the buffering type. 0 Single buffered transmit message buffer 1 Double buffered transmit message buffer Message Buffer Transfer Direction -- This bit defines the transfer direction of the message buffer. 0 Receive message buffer 1 Transmit message buffer
13 MBT 12 MTD
MFR4300 Data Sheet, Rev. 3 128 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-75. MBCCSRn Field Descriptions (Sheet 2 of 3)
Field Description Message Buffer Control 11 CMT Commit for Transmission -- This bit applies only to transmit message buffers and indicates whether the message buffer contains valid data that are ready for transmission. Both the application and the FlexRay module can modify this bit. * Application: The application sets this bit to indicate that the transmit message buffer contains valid data ready for transmission. The application clears this bit to indicate that the message buffer data are no longer valid for transmission. * FlexRay module: The FlexRay module clears this bit when the message buffer data are no longer valid for transmission. 0 Message buffer does not contain valid data. 1 Message buffer contains valid data. Enable/Disable Trigger -- This trigger bit is used to enable and disable a message buffer. The message buffer enable is triggered when the application writes `1' to this bit and the message buffer is disabled, i.e. the EDS status bit is `0'. The message buffer disable is triggered when the application writes `1' to this bit and the message buffer is enabled, i.e. the EDS status bit is `1'. 0 No effect 1 message buffer enable/disable triggered Note: If the application writes `1' to this bit, the write access to all other bits is ignored. Lock/Unlock Trigger -- This trigger bit is used to lock and unlock a message buffer. The message buffer lock is triggered when the application writes `1' to this bit and the message buffer is not locked, i.e. the LCKS status bit is `0'. The message buffer unlock is triggered when the application writes `1' to this bit and the message buffer is locked, i.e. the LCKS status bit is `1'. 0 No effect 1 Trigger message buffer lock/unlock Note: If the application writes `1' to this bit and `0' to the EDT bit, the write access to all other bits is ignored. Message Buffer Interrupt Enable -- This control bit defines whether the message buffer will generate an interrupt request when its MBIF flag is set. 0 Interrupt request generation disabled 1 Interrupt request generation enabled Message Buffer Status 4 DUP Data Updated -- This status bit applies only to receive message buffers. It is always `0' for transmit message buffers. This bit provides information whether the frame header in the message buffer header field and the message buffer data field were updated. See Section 3.4.6.3.4, "Message Buffer Status Update" for a detailed description of the update condtions. 0 Frame Header and Message buffer data field not updated. 1 Frame Header and Message buffer data field updated. Data Valid -- The semantic of this status bit depends on the message buffer type and transfer direction. * Receive Message Buffer: Indicates whether the message buffer data field contains valid frame data. See Section 3.4.6.3.4, "Message Buffer Status Update" for a detailed update description of the update conditions. 0 message buffer data field contains no valid frame data 1 message buffer data field contains valid frame data * Single Transmit Message Buffer: Indicates whether the message is transferred again due to the state transmission mode of the message buffer. 0 Message transferred for the first time. 1 Message will be transferred again. * Double Transmit Message Buffer: For the commit side it is always `0'. For the transmit side it indicates whether the message is transferred again due to the state transmission mode of the message buffer. 0 Message transferred for the first time. 1 Message will be transferred again.
10 EDT
9 LCKT
8 MBIE
3 DVAL
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 129
FlexRay Module (FLEXRAYV2)
Table 3-75. MBCCSRn Field Descriptions (Sheet 3 of 3)
Field 2 EDS 1 LCKS 0 MBIF Description Enable/Disable Status -- This status bit indicates whether the message buffer is enabled or disabled. 0 Message buffer is disabled. 1 Message buffer is enabled. Lock Status -- This status bit indicates the current lock status of the message buffer. 0 Message buffer is not locked by the application. 1 Message buffer is locked by the application. Message Buffer Interrupt Flag -- The semantic of this flag depends on the message buffer transfer direction. * Receive Message Buffer: This flag is set when the slot status in the message buffer header field was updated and this slot was not an empty dynamic slot. See Section 3.4.6.3.4, "Message Buffer Status Update" for a detailed description of the update conditions. 0 slot status not updated 1 slot status updated and slot was not an empty dynamic slot * Transmit Message Buffer: This flag is set when the slot status in the message buffer header field was updated. Additionally this flag is set immediately when a transmit message buffer was enabled. 0 slot status not updated 1 slot status updated / message buffer just enabled Writing a '1' clears this flag. Writing a `0' will not change the flag state.
3.3.2.65
15
Message Buffer Cycle Counter Filter Registers (MBCCFRn)
Write: POC:config or MB_DIS
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
0x0102, 0x010A,..., 0x04FA R W Reset
MTM
CHA
CHB CCFE
CCFMSK
CCFVAL
bits located in physical memory, not affected by reset, no reset value
Figure 3-94. Message Buffer Cycle Counter Filter Registers (MBCCFRn)
This register contains message buffer configuration data for the transmission mode, the channel assignment, and for the cycle counter filtering. For detailed information on cycle counter filtering, refer to Section 3.4.7.1.2, "Message Buffer Cycle Counter Filtering".
Table 3-76. MBCCFRn Field Descriptions
Field 15 MTM Description Message Buffer Transmission Mode -- This control bit applies only to transmit message buffers and defines the transmission mode. 0 Event transmission mode 1 State transmission mode Channel Assignment -- These control bits define the channel assignment and control the receive and transmit behavior of the message buffer according to Table 3-77. Cycle Counter Filtering Enable -- This control bit is used to enable and disable the cycle counter filtering. 0 Cycle counter filtering disabled 1 Cycle counter filtering enabled Cycle Counter Filtering Mask -- This field defines the filter mask for the cycle counter filtering. Cycle Counter Filtering Value -- This field defines the filter value for the cycle counter filtering.
14-13 CHA CHB 12 CCFE 11-6 CCFMSK 5-0 CCFVAL
MFR4300 Data Sheet, Rev. 3 130 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
.
Table 3-77. Channel Assignment Description
Transmit Message Buffer Receive Message Buffer static segment dynamic segment store first valid frame received on channel A, ignore channel B store first valid frame received on channel B store first valid frame received on channel A no frame stored CHB static segment 1 1 dynamic segment transmit on both channel A transmit on channel A only store first valid frame and channel B received on either channel A or channel B transmit on channel B transmit on channel A no frame transmission transmit on channel B transmit on channel A no frame transmission store first valid frame received on channel B store first valid frame received on channel A no frame stored
CHA
0 1 0
1 0 0
NOTE If at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigned to this slot have to be assigned to both channels. Otherwise, the message buffer configuration is illegal and the result of the message buffer search is not defined.
3.3.2.66
15
Message Buffer Frame ID Registers (MBFIDRn)
Write: POC:config or MB_DIS
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
0x0104, 0x010C,..., 0x04FC R W Reset 0 0 0 0 0 0 0 0 0 0
FID bits located in physical memory, not affected by reset, no reset value
Figure 3-95. Message Buffer Frame ID Registers (MBFIDRn) Table 3-78. MBFIDRn Field Descriptions
Field 10-0 FID Description Frame ID -- The semantic of this field depends on the message buffer transfer type. For receive message buffers it is used as a filter value to determine whether or not the message buffer is used for reception of a message received in a slot with the slot ID equal to FID. For a transmit message buffer it is used to determine the slot in which the message in this message buffer will be transmitted.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 131
FlexRay Module (FLEXRAYV2)
3.3.2.67
15
Message Buffer Index Registers (MBIDXRn)
Write: POC:config or MB_DIS
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
0x0106, 0x010E,..., 0x04FE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MBIDX bits located in physical memory, not affected by reset, no reset value
Figure 3-96. Message Buffer Index Registers (MBIDXRn) Table 3-79. MBIDXRn Field Descriptions
Field 7-0 MBIDX Description Message Buffer Index -- This field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. The application writes the index of the initially associated message buffer header field into this register. The FlexRay module updates this register after frame reception or transmission.
MFR4300 Data Sheet, Rev. 3 132 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.4
Functional Description
This section provides a detailed description of the functionality implemented in the FlexRay module.
3.4.1
Message Buffer Concept
The FlexRay module uses a data structure called message buffer to store frame data, configuration, control, and status data. Each message buffer consists of two parts, the message buffer control data and the physical message buffer. The message buffer control data are located in dedicated registers. The structure of the message buffer control data depends on the message buffer type and is described in Section 3.4.3, "Message Buffer Types". The physical message buffer is located in the FRM and is described in Section 3.4.2, "Physical Message Buffer".
3.4.2
Physical Message Buffer
All FlexRay messages and related frame and slot status information of received frames and of frames to be transmitted to the FlexRay bus are stored in data structures called physical message buffers. The physical message buffers are located in the FRM.The structure of a physical message buffer is depicted in Figure 3-97. A physical message buffer consists of two fields, the message buffer header field and the message buffer data field. The message buffer header field contains the frame header, the data field offset, and the slot status.The message buffer data field contains the frame data. The connection between the two fields is established by the data field offset.
SADR_MBDF
Frame Data
FRM
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
Figure 3-97. Physical Message Buffer Structure
3.4.2.1
Message Buffer Header Field
The message buffer header field is a contiguous region in the FRM and occupies ten bytes. It contains the frame header, the data field offset, and the slot status. Its structure is shown in Figure 3-97. The physical start address SADR_MBHF of the message buffer header field must be 16-bit aligned. 3.4.2.1.1 Frame Header
The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay frame header related information according to the FlexRay Communications System Protocol
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 133
FlexRay Module (FLEXRAYV2)
Specification, Version 2.1. A detailed description of the usage and the content of the frame header is provided in Section 3.4.5.2.1, "Frame Header Section Description". 3.4.2.1.2 Data Field Offset
The data field offset follows the frame header in the message buffer data field and occupies two bytes. It contains the offset of the corresponding message buffer data field with respect to the FlexRay module FRM base address 0x800. The data field offset is used to determine the start address SADR_MBDF of the corresponding message buffer data field in the FRM according to Equation 3-1.
SADR_MBDF = [Data Field Offset] + 0x800 Eqn. 3-1
3.4.2.1.3
Slot Status
The slot status occupies the last two bytes of the message buffer header field. It provides the slot and frame status related information according to the FlexRay Communications System Protocol Specification, Version 2.1. A detailed description of the content and usage of the slot status is provided in Section 3.4.5.2.3, "Slot Status Description".
3.4.2.2
Message Buffer Data Field
The message buffer data field is a contiguous area of 2-byte entities. This field contains the frame payload data, or a part of it, of the frame to be transmitted to or received from the FlexRay bus. The minimum length of this field depends on the specific message buffer configuration and is specified in the message buffer descriptions given in Section 3.4.3, "Message Buffer Types".
3.4.3
Message Buffer Types
The FlexRay module provides three different types of message buffers. * Individual Message Buffers * Receive Shadow Buffers * Receive FIFO Buffers For each message buffer type the structure of the physical message buffer is identical. The message buffer types differ only in the structure and content of message buffer control data, which control the related physical message buffer. The message buffer control data are described in the following sections.
3.4.3.1
Individual Message Buffers
The individual message buffers are used for all types of frame transmission and for dedicated frame reception based on individual filter settings for each message buffer. The FlexRay module supports three types of individual message buffers, which are described in Section 3.4.6, "Individual Message Buffer Functional Description". Each individual message buffer consists of two parts, the physical message buffer, which is located in the FRM, and the message buffer control data, which are located in dedicated registers. The structure of an individual message buffer is given in Figure 3-98.
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FlexRay Module (FLEXRAYV2)
Each individual message buffer has a message buffer number n assigned, which determines the set of message buffer control registers associated to this individual message buffer. The individual message buffer with message buffer number n is controlled by the registers MBCCSRn, MBCCFRn, MBFIDRn, and MBIDXRn. The connection between the message buffer control registers and the physical message buffer is established by the message buffer index field MBIDX in the Message Buffer Index Registers (MBIDXRn). The start address SADR_MBHF of the related message buffer header field in the FRM is determined according to Equation 3-2.
SADR_MBHF = (MBIDXRn.MBIDX * 10) + 0x800
>= MBDSR.MBSEG[1,2] * 2 bytes
SADR_MBDF
Eqn. 3-2
FrameData
FRM
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
MBCCSRn
MBCCFRn
MBFIDRn
MBIDXRn
Message Buffer Control Registers
Figure 3-98. Individual Message Buffer Structure
3.4.3.1.1
Individual Message Buffer Segments
The set of the individual message buffers can be split up into two message buffer segments using the Message Buffer Segment Size and Utilization Register (MBSSUTR). All individual message buffers with a message buffer number n <= MBSSUTR.LAST_MB_SEG1 belong to the first message buffer segment. All individual message buffers with a message buffer number n > MBSSUTR.LAST_MB_SEG1 belong to the second message buffer segment. The following rules apply to the length of the message buffer data field: * all physical message buffers associated to individual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length * the minimum length of the message buffer data field for individual message buffers in the first message buffer segment is 2 * MBDSR.MBSEG1DS bytes * the minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 * MBDSR.MBSEG2DS bytes.
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3.4.3.2
Receive Shadow Buffers
The receive shadow buffers are required for the frame reception process for individual message buffers. The FlexRay module provides four receive shadow buffers, one receive shadow buffer per channel and per message buffer segment. Each receive shadow buffer consists of two parts, the physical message buffer located in the FRM and the receive shadow buffer control registers located in dedicated registers. The structure of a receive shadow buffer is shown in Figure 3-99. The four internal shadow buffer control registers can be accessed by the Receive Shadow Buffer Index Register (RSBIR). The connection between the receive shadow buffer control register and the physical message buffer for the selected receive shadow buffer is established by the receive shadow buffer index field RSBIDX in the Receive Shadow Buffer Index Register (RSBIR). The start address SADR_MBHF of the related message buffer header field in the FRM is determined according to Equation 3-3.
SADR_MBHF = (RSBIR.RSBIDX * 10) + 0x800 Eqn. 3-3
The length required for the message buffer data field depends on the message buffer segment that the receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer segment, the length must be the same as for the individual message buffers assigned to the first message buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length must be the same as for the individual message buffers assigned to the second message buffer segment. The receive shadow buffer assignment is described in Receive Shadow Buffer Index Register (RSBIR).
>= MBDSR.MBSEG[1,2] * 2 bytes
SADR_MBDF
Frame Data
Message Buffer Data Field FRM
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
RSBIDX_0
RSBIDX_1 RSBIDX_2 RSBIDX_3
Receive Shadow Buffer Control Register
Figure 3-99. Receive Shadow Buffer Structure
3.4.3.3
Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The FlexRay module provides two independent receive FIFOs, one per channel.
MFR4300 Data Sheet, Rev. 3 136 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
A receive FIFO consists of a set of physical message buffers in the FRM and a set of receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in Figure 3-100. The connection between the receive FIFO control registers and the set of physical message buffers is established by the start index field SIDX in the Receive FIFO Start Index Register (RFSIR), the FIFO depth field FIFO_DEPTH in the Receive FIFO Depth and Size Register (RFDSR), and the read index field RDIDX Receive FIFO A Read Index Register (RFARIR) / Receive FIFO B Read Index Register (RFBRIR). The start address SADR_MBHF_1 of the first message buffer header field that belongs to the receive FIFO in the FRM is determined according to Equation 3-4.
SADR_MBHF_1 = (RFSIR.SIDX * 10) + 0x800 Eqn. 3-4
The start address SADR_MBHF_n of the last message buffer header field that belongs to the receive FIFO in the FRM is determined according to Equation 3-5.
SADR_MBHF_n = ((RFSIR.SIDX+RFDSR.FIFO_DEPTH) * 10) + 0x800 Eqn. 3-5
NOTE All message buffer header fields assigned to a receive FIFO must be a contiguous region.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 137
FlexRay Module (FLEXRAYV2)
>= RFDSR.ENTRY_SIZE * 2 bytes
SADR_MBDF_n RFDSR.FIFO_DEPTH
FrameData n
SADR_MBDF_i
FrameData i
SADR_MBDF_1
FrameData 1
FRM
Message Buffer Data Fields
SADR_MBHF_n RFDSR.FIFO_DEPTH
+
SADR_MBHF_i
Frame Header n
Data Field Offset n
Slot Status n
Frame Header i
SADR_MBHF_1
Data Field Offset i
Slot Status i
Frame Header 1
Data Field Offset 1
Slot Status 1
Message Buffer Header Fields
RFDSR RFSIR
RFSIR RFDSR
RFARIR RFARIR
Receive FIFO Control Register
Figure 3-100. Receive FIFO Structure
3.4.3.4
Message Buffer Configuration and Control Data
This section describes the configuration and control data for each message buffer type. 3.4.3.4.1 Individual Message Buffer Configuration Data
Before an individual message buffer can be used for transmission or reception, it must be configured. There is a set of common configuration parameters that applies to all individual message buffers and a set of configuration parameters that applies to each message buffer individually. Common Configuration Data The set of common configuration data for individual message buffers is located in the following registers.
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FlexRay Module (FLEXRAYV2)
*
*
Message Buffer Data Size Register (MBDSR) The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data field with respect to the message buffer segment. Message Buffer Segment Size and Utilization Register (MBSSUTR) The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual message buffers and the number of individual message buffers that are used. For more details, see Section 3.4.3.1.1, "Individual Message Buffer Segments"
Specific Configuration Data The set of message buffer specific configuration data for individual message buffers is located in the following registers. * Message Buffer Configuration, Control, Status Registers (MBCCSRn) The MCM, MBT, MTD bits configure the message buffer type. * Message Buffer Cycle Counter Filter Registers (MBCCFRn) The MTM, CHA, CHB bits configure the transmission mode and the channel assignment. The CCFE, CCFMSK, and CCFVAL bits and fields configure the cycle counter filter. * Message Buffer Frame ID Registers (MBFIDRn) For a transmit message buffer, the FID field is used to determine the slot in which the message in this message buffer will be transmitted. * Message Buffer Index Registers (MBIDXRn) This MBIDX field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer.
3.4.3.5
Individual Message Buffer Control Data
During normal operation, each individual message buffer can be controlled by the control and trigger bits CMT, LCKT, EDT, and MBIE in the Message Buffer Configuration, Control, Status Registers (MBCCSRn).
3.4.3.6
Receive Shadow Buffer Configuration Data
Before frame reception into the individual message buffers can be performed, the receive shadow buffers must be configured. The configuration data are provided by the Receive Shadow Buffer Index Register (RSBIR). For each receive shadow buffer, the application provides the message buffer header index. When the protocol is in the POC:normal active or POC:normal passive state, the receive shadow buffers are under full FlexRay module control.
3.4.3.7
Receive FIFO Control and Configuration Data
This section describes the configuration and control data for the two receive FIFOs. 3.4.3.7.1 Receive FIFO Configuration Data
The FlexRay module provides two completely independent receive FIFOs, one per channel. Each FIFO has its own set of configuration data. The configuration data are located in the following registers:
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 139
FlexRay Module (FLEXRAYV2)
* * * * * * *
Receive FIFO Start Index Register (RFSIR) Receive FIFO Depth and Size Register (RFDSR) Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) Receive FIFO Range Filter Configuration Register (RFRFCFR) Receive FIFO Control Data
3.4.3.7.2
The application can access the receive FIFO at any time using the values provided in the Receive FIFO A Read Index Register (RFARIR) and Receive FIFO B Read Index Register (RFBRIR). To update the Receive FIFO A Read Index Register (RFARIR), the application must write `1' to the FIFO A Not Empty Interrupt Flag FNEAIF in the Global Interrupt Flag and Enable Register (GIFER). To update the Receive FIFO B Read Index Register (RFBRIR) the application must write `1' to the FIFO B Not Empty Interrupt Flag FNEBIF in the Global Interrupt Flag and Enable Register (GIFER). Each update increments the related read index. If the read index has reached the last FIFO entry, it wraps back to the FIFO start index. NOTE The read index is incremented or wrapped on each update, even if the FIFO is empty. The update of an empty fifo results in an non-empty FIFO and the FIFO non-empty FIFO is set to `1'.
3.4.4
FlexRay Memory Layout
The FlexRay module supports a wide range of possible layouts for the FRM. Figure 3-101 shows an example layout. The following set of rules applies to the layout of the FRM: * The FRM is a contiguous region. * The maximum size of the FRM is 6 Kbytes. * The FRM starts at address 0x800. The FRM contains three areas: the message buffer header area, the message buffer data area, and the sync frame table area. The areas are described in this section.
MFR4300 Data Sheet, Rev. 3 140 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Device Memory
Sync Frame Table Area
Message Buffer Data Area
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Area
Message Buffer Header Fields Receive FIFO B
FRM
Frame Header Frame Header
Data Field Offset Data Field Offset
Slot Status Slot Status
Message Buffer Header Fields Receive FIFO A
Frame Header Frame Header Data Field Offset Data Field Offset Slot Status Slot Status
Message Buffer Header Fields Individual Message Buffers Receive Shadow Buffers
Frame Header
Data Field Offset
Slot Status
Frame Header
Data Field Offset
Slot Status
0x800
10 bytes
Figure 3-101. Example of FRM Layout
3.4.4.1
Message Buffer Header Area
The message buffer header area contains all message buffer header fields of the physical message buffers for all message buffer types. The following rules apply to the message buffer header fields for the three type of message buffers. 1. The start address SADR_MBHF of each message buffer header field for individual message buffers and receive shadow buffers must fulfill Equation 3-6.
SADR_MBHF = (i * 10) + 0x800; (0 <= i <132) Eqn. 3-6
2. The start address SADR_MBHF of each message buffer header field for the receive FIFO must fulfill Equation 3-7.
SADR_MBHF = (i * 10) + 0x800; (0 <= i < 1024) Eqn. 3-7
3. The message buffer header fields for a receive FIFO have to be a contiguous area.
3.4.4.2
Message Buffer Data Area
The message buffer data area contains all the message buffer data fields of the physical message buffers. Each message buffer data field must start at a 16-bit boundary.
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FlexRay Module (FLEXRAYV2)
3.4.4.3
Sync Frame Table Area
The sync frame table area is used to provide a copy of the internal sync frame tables for application access. Refer to Section 3.4.12, "Sync Frame ID and Sync Frame Deviation Tables" for the description of the sync frame table area.
3.4.5
Physical Message Buffer Description
This section provides a detailed description of the usage and the content of the two parts of a physical message buffer, the message buffer header field and the message buffer data field.
3.4.5.1
Message Buffer Protection and Data Consistency
The physical message buffers are located in the FRM. The FlexRay module provides no means to protect the FRM from uncontrolled or illegal host or other client write access. To ensure data consistency of the physical message buffers, the application must follow the write access scheme that is given in the description of each of the physical message buffer fields.
3.4.5.2
Message Buffer Header Field Description
This section provides a detailed description of the usage and content of the message buffer header field. A description of the structure of the message buffer header fields is given in Section 3.4.2.1, "Message Buffer Header Field". Each message buffer header field consists of three sections: the frame header section, the data field offset, and the slot status section. For a detailed description of the Data Field Offset, see Section 3.4.2.1.2, "Data Field Offset". 3.4.5.2.1 Frame Header Section Description
Frame Header Section Content The semantic and content of the frame header section depends on the message buffer type. For individual receive message buffers and receive FIFOs, the frame header receives the frame header data of the first valid frame received on the assigned channels. If a receive message buffer is assigned to both channels, the first valid frame received on either channel A or channel B is stored. For receive shadow buffers, the frame header receives the frame header data of the current frame received regardless of whether the frame is valid or not. For single and double transmit message buffers, the application writes the frame header of the frame to be transmitted into this location. The frame header will be read out when the frame is transferred to the FlexRay bus. The structure of the frame header in the message buffer header field is given in Figure 3-102. A detailed description of the frame header fields is given in Table 3-81.
MFR4300 Data Sheet, Rev. 3 142 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 0x2 0x4
R*
PPI
NUF
SYF
SUF CYCCNT
FID PLDLEN HDCRC
= not used for TX message buffers, not updated for RX message buffers
Figure 3-102. Frame Header Structure
Frame Header Section Access The frame header is located in the FRM. To ensure data consistency, the application must follow the write access scheme described below. For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to the frame header field. For transmit message buffers, the application must follow the write access restrictions given in Table 3-80. This table shows the condition under which the application can write to the frame header entries. In general, the application can modify all frame header entries when the protocol is in the POC:config state or when the message buffer is disabled. For message buffers assigned to the dynamic segment, the application can modify all frame header entries except the frame ID when the message buffer is locked.
Table 3-80. Frame Header Write Access Constraints
TX Single Buffered Field Static Segment Dynamic Segment Static Segment Commit Side Transmit Side Dynamic Segment Commit Side Transmit Side Double Buffered
FID R*, PPI NUF, SYF SUF CYCCNT PLDLEN HDCRD
POC:config or MB_DIS
POC:config or MB_DIS
POC:config or MB_DIS or MB_LCK
POC:config or MB_DIS
POC:config or MB_DIS or MB_LCK
POC:config or MB_DIS
The frame header entries NUF, SYF, SUF, and CYCCNT are not used for frame transmission. These values are generated internally before frame transmission depending on the current transmission state and configuration. For transmit message buffers assigned to the static segment, the PLDLEN value must be equal to the value of the payload_length_static field in the Protocol Configuration Register 19 (PCR19). If this is not fulfilled, the static payload length error flag SPL_EF in the CHI Error Flag Register (CHIERFR) is set when the message buffer is under transmission. The PE generates a syntactically and semantically correct frame with payload_length_static payload words and the payload length field in the frame header set to payload_length_static.
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FlexRay Module (FLEXRAYV2)
For transmit message buffers assigned to the dynamic segment, the PLDLEN value must be less than or equal to the value of the max_payload_length_dynamic field in the Protocol Configuration Register 24 (PCR24). If this is not fulfilled, the dynamic payload length error flag DPL_EF in the CHI Error Flag Register (CHIERFR) is set when the message buffer is under transmission. The PE generates a syntactically and semantically correct dynamic frame with PLDLEN payload words and the payload length field in the frame header set to PLDLEN.
Table 3-81. Frame Header Field Descriptions
Field R* Description Reserved Bit -- This bit corresponds to the Reserved bit in the FlexRay frame header. * For receive and FIFO message buffers, this is a status bit and represents the value of the Reserved bit in the frame received on the FlexRay bus in the corresponding slot. * For transmit message buffers, this is a control bit. The FlexRay module transmits this within the frame header. Note: For protocol compliant operation, this control bit must be set to `0' for transmit message buffers. Payload Preamble Indicator -- This bit corresponds to the Payload Preamble Indicator in the FlexRay frame header. * For receive and FIFO message buffers, this is a status bit and represents the value of the Payload Preamble Indicator of the first valid frame received on the FlexRay in the slot indicated by the CYCCNT field. * For transmit message buffers, this is a control bit. The FlexRay module uses this value to set the Payload Preamble Indicator in the frame header of the frame to transmit. 0 No network management vector or message ID in frame payload data 1 Static Segment: Frame payload data contains network management vector Dynamic Segment: Frame payload data contains message ID Null Frame Indicator -- This bit corresponds to the Null Frame Indicator in the FlexRay frame header. * For receive message buffers and receive FIFOs, this is a status bit and represents the value of the Null Frame Indicator of the first valid frame received on the FlexRay bus in the slot indicated by the CYCCNT field. * For transmit message buffers, the value of this bit is ignored. The FlexRay module determines internally whether a null frame or non-null frame must be transmitted and sets the Null Frame Indicator accordingly. 0 Null frame received 1 Normal frame received Sync Frame Indicator -- This bit corresponds to the Sync Frame Indicator in the FlexRay frame header. * For receive message buffers and receive FIFOs, this is a status bit and represents the value of the Sync Frame Indicator of the first valid frame received on the FlexRay bus in the slot indicated by the CYCCNT field. * For transmit message buffers, the value of this bit is ignored. The FlexRay module determines internally whether a sync frame must be transmitted and sets the Sync Frame Indicator accordingly. Startup Frame Indicator -- This bit corresponds to the Startup Frame Indicator in the FlexRay frame header. * For receive message buffers and receive FIFOs, this is a status bit and represents the value of the Startup Frame Indicator of the first valid frame received on the FlexRay bus in the slot indicated by the CYCCNT field * For transmit message buffers, the value of this bit is ignored. The FlexRay module determines internally whether a startup frame must be transmitted and sets the Startup Frame Indicator accordingly. Frame ID * For receive message buffers and receive FIFOs, this field provides the value of the Frame ID field of the first valid frame received on the FlexRay bus in the slot indicated by the CYCCNT field. * For transmit message buffers, this field provides the value that will be transmitted in the Frame ID field of the FlexRay frame. Note: For transmit message buffers, the application must program this field to the same value as in the corresponding Message Buffer Frame ID Registers (MBFIDRn). If the FlexRay module detects a mismatch while transmitting the frame header, it will set the frame ID error flag FID_EF in the CHI Error Flag Register (CHIERFR). The value of the FID field will be ignored and replaced by the value provided in the Message Buffer Frame ID Registers (MBFIDRn).
PPI
NUF
SYF
SUF
FID
MFR4300 Data Sheet, Rev. 3 144 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-81. Frame Header Field Descriptions (Continued)
Field CYCCNT Description Cycle Count * For receive message buffer and receive FIFOs, this field provides the number of the communication cycle in which the frame stored in this message buffer was received. * For transmit message buffers, the value of this field is ignored. The FlexRay module will overwrite this value with the current cycle count value when it transmits the frame. Payload Length in 16-Bit Units * For receive message buffers and receive FIFOs, this field provides the value of the payload length field of the first valid frame received on the FlexRay bus in the slot indicated by the FID field. * For transmit message buffers assigned to the static segment, this value is ignored for the frame generation. The FlexRay module uses the value in the PCR19.paylaod_length_static to set the value of the Payload length field in the transmitted frame. * For transmit message buffers assigned to the dynamic segment, this value is used to set the value of the Payload length field in the transmitted frame. Note: The value of this field is given in numbers of 16-bit units Header CRC * For receive and FIFO message buffers, this field provides the value of the Header CRC of the received frame. * For transmit message buffers, this field provides the Header CRC value as it was given by the application.The FlexRay module transmits this value in the Header CRC field of the transmitted frame.
PLDLEN
HDCRC
3.4.5.2.2
Data Field Offset Description
Data Field Offset Content For a detailed description of the Data Field Offset, see Section 3.4.2.1.2, "Data Field Offset". Data Field Offset Access The application shall program the Data Field Offset when configuring the message buffers either in the POC:config state or when the message buffer is disabled. 3.4.5.2.3 Slot Status Description
The slot status is a read-only structure for the application and a write-only structure for the FlexRay module. The meaning and content of the slot status in the message buffer header field depends on the message buffer type. Receive Message Buffer and Receive FIFO Slot Status Description This section describes the slot status structure for the individual receive message buffers and receive FIFOs. The content of the slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by Table 3-82.
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FlexRay Module (FLEXRAYV2)
Table 3-82. Receive Message Buffer Slot Status Content
Receive Message Buffer Type Individual Receive Message Buffer assigned to both channels MBCCSRn.CHA='1' and MBCCSRn.CHB='1' Individual Receive Message Buffer assigned to channel A MBCCSRn.CHA='1' and MBCCSRn.CHB='0' Individual Receive Message Buffer assigned to channel B MBCCSRn.CHA='0' and MBCCSRn.CHB='1' Receive FIFO Channel A Message Buffer Receive FIFO Channel B Message Buffer Slot Status Content see Figure 3-103 see Figure 3-104 see Figure 3-105 see Figure 3-104 see Figure 3-105
The meaning of the bits in the slot status structure is explained in Table 3-83.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VFB Reset -
SYB -
NFB -
SUB -
SEB -
CEB -
BVB -
CH -
VFA -
SYA -
NFA -
SUA -
SEA -
CEA -
BVA -
0 -
Figure 3-103. Receive Message Buffer Slot Status Structure (ChAB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reset
0 -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
VFA -
SYA -
NFA -
SUA -
SEA -
CEA -
BVA -
0 -
Figure 3-104. Receive Message Buffer Slot Status Structure (ChA)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VFB Reset -
SYB -
NFB -
SUB -
SEB -
CEB -
BVB -
1 -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
Figure 3-105. Receive Message Buffer Slot Status Structure (ChB) Table 3-83. Receive Message Buffer Slot Status Field Descriptions
Field Description Common Message Buffer Status Bits 15 VFB 14 SYB 13 NFB 12 SUB Valid Frame on Channel B -- protocol related variable: vSS!ValidFrame channel B 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel B -- protocol related variable: vRF!Header!SyFIndicator channel B 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1' Null Frame Indicator Channel B -- protocol related variable: vRF!Header!NFIndicator channel B 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel B -- protocol related variable: vRF!Header!SuFIndicator channel B 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1'
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FlexRay Module (FLEXRAYV2)
Table 3-83. Receive Message Buffer Slot Status Field Descriptions (Continued)
Field 11 SEB 10 CEB 9 BVB 8 CH Description Syntax Error on Channel B -- protocol related variable: vSS!SyntaxError channel B 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel B -- protocol related variable: vSS!ContentError channel B 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' Boundary Violation on Channel B -- protocol related variable: vSS!BViolation channel B 0 vSS!BViolation = `0' 1 vSS!BViolation = `1' Channel first valid received -- This status bit applies only to receive message buffers assigned to the static segment and to both channels. It indicates the channel that has received the first valid frame in the slot. This flag is set to `0' if no valid frame was received at all in the subscribed slot. 0 first valid frame received on channel A, or no valid frame received at all 0 first valid frame received on channel B Valid Frame on Channel A -- protocol related variable: vSS!ValidFrame channel A 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel A -- protocol related variable: vRF!Header!SyFIndicator channel A 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1' Null Frame Indicator Channel A -- protocol related variable: vRF!Header!NFIndicator channel A 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel A -- protocol related variable: vRF!Header!SuFIndicator channel A 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1' Syntax Error on Channel A -- protocol related variable: vSS!SyntaxError channel A 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel A -- protocol related variable: vSS!ContentError channel A 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' Boundary Violation on Channel A -- protocol related variable: vSS!BViolation channel A 0 vSS!BViolation = `0' 1 vSS!BViolation = `1'
7 VFA 6 SYA 5 NFA 4 SUA 3 SEA 2 CEA 1 BVA
Transmit Message Buffer Slot Status Description This section describes the slot status structure for transmit message buffers. Only the TCA and TCB status bits are directly related to the transmission process. All other status bits in this structure are related to a receive process that may have occurred. The content of the slot status structure for transmit message buffers depends on the channel assignment as given by Table 3-84.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 147
FlexRay Module (FLEXRAYV2)
Table 3-84. Transmit Message Buffer Slot Status Content
Transmit Message Buffer Type Individual Transmit Message Buffer assigned to both channels MBCCSRn.CHA='1' and MBCCSRn.CHB='1' Individual Transmit Message Buffer assigned to channel A MBCCSRn.CHA='1' and MBCCSRn.CHB='0' Individual Transmit Message Buffer assigned to channel B MBCCSRn.CHA='0' and MBCCSRn.CHB='1' Slot Status Content see Figure 3-106 see Figure 3-107 see Figure 3-108
The meaning of the bits in the slot status structure is described in Table 3-83.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VFB Reset -
SYB -
NFB -
SUB -
SEB -
CEB -
BVB -
TCB -
VFA -
SYA -
NFA -
SUA -
SEA -
CEA -
BVA -
TCA -
Figure 3-106. Transmit Message Buffer Slot Status Structure (ChAB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reset
0 -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
VFA -
SYA -
NFA -
SUA -
SEA -
CEA -
BVA -
TCA -
Figure 3-107. Transmit Message Buffer Slot Status Structure (ChA)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VFB Reset -
SYB -
NFB -
SUB -
SEB -
CEB -
BVB -
TCB -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
0 -
Figure 3-108. Transmit Message Buffer Slot Status Structure (ChB) Table 3-85. Transmit Message Buffer Slot Status Structure Field Descriptions
Field 15 VFB 14 SYB 13 NFB 12 SUB 11 SEB 10 CEB Description Valid Frame on Channel B -- protocol related variable: vSS!ValidFrame channel B 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel B -- protocol related variable: vRF!Header!SyFIndicator channel B 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1' Null Frame Indicator Channel B -- protocol related variable: vRF!Header!NFIndicator channel B 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel B -- protocol related variable: vRF!Header!SuFIndicator channel B 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1' Syntax Error on Channel B -- protocol related variable: vSS!SyntaxError channel B 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel B -- protocol related variable: vSS!ContentError channel B 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' MFR4300 Data Sheet, Rev. 3 148 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-85. Transmit Message Buffer Slot Status Structure Field Descriptions (Continued)
Field 9 BVB 8 TCB 7 VFA 6 SYA 5 NFA 4 SUA 3 SEA 2 CEA 1 BVA 0 TCA Description Boundary Violation on Channel B -- protocol related variable: vSS!BViolation channel B 0 vSS!BViolation = `0' 1 vSS!BViolation = `1' Transmission Conflict on Channel B -- protocol related variable: vSS!TxConflict channel B 0 vSS!TxConflict = `0' 1 vSS!TxConflict = `1' Valid Frame on Channel A -- protocol related variable: vSS!ValidFrame channel A 0 vSS!ValidFrame = `0' 1 vSS!ValidFrame = `1' Sync Frame Indicator Channel A -- protocol related variable: vRF!Header!SyFIndicator channel A 0 vRF!Header!SyFIndicator = `0' 1 vRF!Header!SyFIndicator = `1' Null Frame Indicator Channel A -- protocol related variable: vRF!Header!NFIndicator channel A 0 vRF!Header!NFIndicator = `0' 1 vRF!Header!NFIndicator = `1' Startup Frame Indicator Channel A -- protocol related variable: vRF!Header!SuFIndicator channel A 0 vRF!Header!SuFIndicator = `0' 1 vRF!Header!SuFIndicator = `1' Syntax Error on Channel A -- protocol related variable: vSS!SyntaxError channel A 0 vSS!SyntaxError = `0' 1 vSS!SyntaxError = `1' Content Error on Channel A -- protocol related variable: vSS!ContentError channel A 0 vSS!ContentError = `0' 1 vSS!ContentError = `1' Boundary Violation on Channel A -- protocol related variable: vSS!BViolation channel A 0 vSS!BViolation = `0' 1 vSS!BViolation = `1' Transmission Conflict on Channel A -- protocol related variable: vSS!TxConflict channel A 0 vSS!TxConflict = `0' 1 vSS!TxConflict = `1'
3.4.5.3
Message Buffer Data Field Description
The message buffer data field is used to store the frame payload data, or a part of it, of the frame to be transmitted to or received from the FlexRay bus. The minimum required length of this field depends on the message buffer type that the physical message buffer is assigned to and is given in Table 3-86. The structure of the message buffer data field is given in Figure 3-109.
Table 3-86. Message Buffer Data Field Minimum Length
physical message buffer assigned to Individual Message Buffer in Segment 1 Receive Shadow Buffer in Segment 1 Individual Message Buffer in Segment 2 Receive Shadow Buffer in Segment 2 Receive FIFO for channel A minimum length defined by MBDSR.MBSEG1DS MBDSR.MBSEG1DS MBDSR.MBSEG2DS MBDSR.MBSEG2DS RFDSR.ENTRY_SIZE (RFSR.SEL = 0)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 149
FlexRay Module (FLEXRAYV2)
Table 3-86. Message Buffer Data Field Minimum Length
physical message buffer assigned to Receive FIFO for channel B minimum length defined by RFDSR.ENTRY_SIZE (RFSR.SEL = 1)
NOTE The FlexRay module will not access any locations outside the message buffer data field boundaries given by Table 3-86.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0 0x2 ... 0xN-2
DATA0 / MID0 / NMV0 DATA2 / NMV2 ... DATA N-2
DATA1 / MID1 / NMV1 DATA3 / NMV3 ... DATA N-1
Figure 3-109. Message Buffer Data Field Structure
The message buffer data field is located in the FRM; thus, the FlexRay module has no means to control application write access to the field. To ensure data consistency, the application must follow a write and read access scheme. 3.4.5.3.1 Message Buffer Data Field Read Access
For transmit message buffers, the FlexRay module will not modify the content of the Message Buffer Data Field. Thus the application can read back the data at any time without any impact on data consistency. For receive message buffers the application must lock the related receive message buffer and retrieve the message buffer header index from the Message Buffer Index Registers (MBIDXRn). While the message buffer is locked, the FlexRay module will not update the Message Buffer Data Field. For receive FIFOs, the application can read the message buffer indicated by the Receive FIFO A Read Index Register (RFARIR) or the Receive FIFO B Read Index Register (RFBRIR) when the related receive FIFO non-empty interrupt flag FNEAIF or FNEBIF is set in the Global Interrupt Flag and Enable Register (GIFER). While the non-empty interrupt flag is set, the FlexRay module will not update the Message Buffer Data Field related to message buffer indicated by Receive FIFO A Read Index Register (RFARIR) or the Receive FIFO B Read Index Register (RFBRIR). 3.4.5.3.2 Message Buffer Data Field Write Access
For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to the message buffer data field. For transmit message buffers, the application must follow the write access restrictions given in Table 3-87.
MFR4300 Data Sheet, Rev. 3 150 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-87. Frame Data Write Access Constraints
double buffered Field single buffered commit side DATA, MID, NMV POC:config or MB_DIS or MB_LCK transmit side
POC:config or MB_DIS POC:config or MB_DIS or MB_LCK
Table 3-88. Frame Data Field Descriptions
Field Description
DATA[0:N-1] Message Data -- Provides the message data received or to be transmitted. For receive message buffer and receive FIFOs, this field provides the message data received for this message buffer. For transmit message buffers, the field provides the message data to be transmitted. MID[0:1] Message Identifier -- If the payload preamble bit PPI is set in the message buffer frame header, the MID field holds the message ID of a dynamic frame located in the message buffer. The receive FIFO filter uses the received message ID for message ID filtering. Network Management Vector -- If the payload preamble bit PPI is set in the message buffer frame header, the network management vector field holds the network management vector of a static frame located in the message buffer. Note: The MID and NMV bytes replace the corresponding DATA bytes.
NMV[0:11]
3.4.6
Individual Message Buffer Functional Description
The FlexRay module provides three basic types of individual message buffers: 1. Single Transmit Message Buffers 2. Double Transmit Message Buffers 3. Receive Message Buffers Before an individual message buffer can be used, it must be configured by the application. After the initial configuration, the message buffer can be reconfigured later. The set of the configuration data for individual message buffers is given in Section 3.4.3.4.1, "Individual Message Buffer Configuration Data".
3.4.6.1
Individual Message Buffer Configuration
The individual message buffer configuration consists of two steps. The first step is the allocation of the required amount of memory for the FRM. The second step is the programming of the message buffer configuration registers, which is described in this section. 3.4.6.1.1 Common Configuration Data
One part of the message buffer configuration data is common to all individual message buffers and the receive shadow buffers. These data can only be set when the protocol is in the POC:config state. The application configures the number of utilized individual message buffers by writing the message buffer number of the last utilized message buffer into the LAST_MB_UTIL field in the Message Buffer Segment Size and Utilization Register (MBSSUTR).
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 151
FlexRay Module (FLEXRAYV2)
The application configures the size of the two segments of individual message buffers by writing the message buffer number of the last message buffer in the first segment into the LAST_MB_SEG1 field in the Message Buffer Segment Size and Utilization Register (MBSSUTR) The application configures the length of the message buffer data fields for both of the message buffer segments by writing to the MBSEG2DS and MBSEG1DS fields in the Message Buffer Data Size Register (MBDSR). Depending on the current receive functionality of the FlexRay module, the application must configure the receive shadow buffers. For each segment and for each channel with at least one individual receive message buffer assigned, the application must configure the related receive shadow buffer using the Receive Shadow Buffer Index Register (RSBIR). 3.4.6.1.2 Specific Configuration Data
The second part of the message buffer configuration data is specific for each message buffer. These data can be changed only when either * the protocol is in the POC:config state or * the message buffer is disabled, i.e. MBCCSRn.EDS = 0 The individual message buffer type is defined by the MTD and MBT bits in the Message Buffer Configuration, Control, Status Registers (MBCCSRn) as given in Table 3-89.
Table 3-89. Individual Message Buffer Types
MBCCSRn.MTD 0 0 1 1 MBCCSRn.MBT 0 1 0 1 Individual Message Buffer Description Receive Message Buffer Reserved Single Transmit Message Buffer Double Transmit Message Buffer
The message buffer specific configuration data are 1. 2. 3. 4. MCM, MBT, MTD bits in Message Buffer Configuration, Control, Status Registers (MBCCSRn) all fields and bits in Message Buffer Cycle Counter Filter Registers (MBCCFRn) all fields and bits in Message Buffer Frame ID Registers (MBFIDRn) all fields and bits in Message Buffer Index Registers (MBIDXRn)
The meaning of the specific configuration data depends on the message buffer type, as given in the detailed message buffer type descriptions Section 3.4.6.2, "Single Transmit Message Buffers", Section 3.4.6.3, "Receive Message Buffers", and Section 3.4.6.4, "Double Transmit Message Buffer".
3.4.6.2
Single Transmit Message Buffers
The section provides a detailed description of the functionality of single buffered transmit message buffers. A single transmit message buffer is used by the application to provide message data to the FlexRay module that will be transmitted over the FlexRay Bus. The FlexRay module uses the transmit message buffers to
MFR4300 Data Sheet, Rev. 3 152 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
provide information about the transmission process and status information about the slot in which message was transmitted. The individual message buffer with message buffer number n is configured to be a single transmit message buffer by the following settings: * MBCCSRn.MBT = `0' (single buffered message buffer) * MBCCSRn.MTD = `1' (transmit message buffer) 3.4.6.2.1 Access Regions
To certain message buffer fields, both the application and the FlexRay module have access. To ensure data consistency, a message buffer locking scheme is implemented, which is used to control the access to the data, control, and status bits of a message buffer. The access regions for single transmit message buffers are depicted in Figure 3-110. A description of the regions is given in Table 3-90. If an region is active as indicated in Table 3-91, the access scheme given for that region applies to the message buffer.
Message Buffer Header Field: Frame Header
CFG NF
Message Buffer Header Field: Data Field Offset MBIDXRn.MBIDX MBCCSRn.CMT
TX
CMT
MSG
Message Buffer Data Field: DATA[0-N] Message Buffer Header Field: Slot Status MBCCSRn.MBT/MTD MBCCFRn.MTM/CHA/CHB/CCF* MBFIDRn.FID
SR
Figure 3-110. Single Transmit Message Buffer Access Regions Table 3-90. Single Transmit Message Buffer Access Regions Description
Access from Region Application CFG MSG NF TX CM SR read/write read/write Module read-only read/write read-only read-only Message Buffer Configuration Message Data and Slot Status Access Message Header Access for Null Frame Transmission Message Transmission and Slot Status Update Message Buffer Validation Message Buffer Search Region used for
The trigger bits MBCCSRn.EDT and MBCCSRn.LCKT, and the interrupt enable bit MBCCSRn.MBIE are not under access control and can be accessed from the application at any time. The status bits
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 153
FlexRay Module (FLEXRAYV2)
MBCCSRn.EDS and MBCCSRn.LCKS are not under access control and can be accessed from the FlexRay module at any time. The interrupt flag MBCCSnR.MBIF is not under access control and can be accessed from the application and the FlexRay module at any time. FlexRay module clear access has higher priority. The FlexRay module restricts its access to the regions depending on the current state of the message buffer. The application must adhere to these restrictions in order to ensure data consistency. The transmit message buffer states are given in Figure 3-111. A description of the states is given in Table 3-91, which also provides the access scheme for the access regions. The status bits MBCCSRn.EDS and MBCCSRn.LCKS provide the application with the required message buffer status information. The internal status information is not visible to the application. 3.4.6.2.2 Message Buffer States
This section describes the transmit message buffer states and provides a state diagram.
RESET_STATE
HD HE HL SU MA SSS
HDis
HL HU
Idle
SA
CCSu
DSS
HDisLck
HE HD HL
CCSa
STS DSS STS
CCTx
HU SA
HLck
MA
DSS
HU
SSS
TX
HLckCCSa
STS HL
CCNf
CCMa
HL
HU SSS
HU STS
HLckCCNf
HLckCCMa
DSS
Figure 3-111. Single Transmit Message Buffer States Table 3-91. Single Transmit Message Buffer State Description (Sheet 1 of 2)
MBCCSRn State EDS Idle HDis HDisLck HLck 1 0 0 1 LCKS 0 0 1 1 Appl. - CFG CFG MSG Module CM, SR - - SR Idle - Message Buffer is idle. Included in message buffer search. Disabled - Message Buffer under configuration. Excluded from message buffer search. Disabled and Locked - Message Buffer under configuration. Excluded from message buffer search. Locked - Applications access to data, control, and status. Included in message buffer search. Access Region Description
MFR4300 Data Sheet, Rev. 3 154 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-91. Single Transmit Message Buffer State Description (Sheet 2 of 2)
MBCCSRn State EDS CCSa HLckCCSa CCNf HLckCCNf CCMa HLckCCMa 1 1 1 1 1 1 LCKS 0 1 0 1 0 1 Appl. - MSG - MSG - MSG Module - - NF NF CM - Slot Assigned - Message buffer assigned to next static slot. Ready for Null Frame transmission. Locked and Slot Assigned - Applications access to data, control, and status.Message buffer assigned to next static slot Null Frame Transmission Header is used for null frame transmission. Locked and Null Frame Transmission - Applications access to data, control, and status. Header is used for null frame transmission. Message Available - Message buffer is assigned to next slot and cycle counter filter matches. Locked and Message Available - Applications access to data, control, and status. Message buffer is assigned to next slot and cycle counter filter matches. Message Transmission - Message buffer data transmit. Payload data from buffer transmitted Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. Access Region Description
CCTx CCSu
1 1
0 0
- -
TX TX
3.4.6.2.3
Message Buffer Transitions
Application Transitions The application transitions can be triggered by the application using the commands described in Table 3-92. The application issues the commands by writing to the Message Buffer Configuration, Control, Status Registers (MBCCSRn). Only one command can be issued with one write access. Each command is executed immediately. If the command is ignored, it must be issued again. The enable and disable commands issued by writing `1' to the trigger bit MBCCSRn.EDT. The transition that will be triggered by each of these command depends on the current value of the status bit MBCCSRn.EDS. If the command triggers the disable transition HD and the message buffer is in one of the states CCSa, HLckCCSa, CCMa, HLckCCMa, CCNf, HLckCCNf, or CCTx, the disable transition has no effect (command is ignored) and the message buffer state is not changed. No notification is given to the application. The lock and unlock commands issued by writing `1' to the trigger bit MBCCSRn.LCKT. The transition that will be triggered by each of these commands depends on the current value of the status bit MBCCSRn.LCKS. If the command triggers the lock transition HL and the message buffer is in the state CCTx, the lock transition has no effect (command is ignored) and message buffer state is not changed. In this case, the message buffer lock error flag LCK_EF in the CHI Error Flag Register (CHIERFR) is set.
Table 3-92. Single Transmit Message Buffer Application Transitions
Transition HE HD Command MBCCSRn.EDT:= 1 Condition Description
MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDS = 1 Application triggers message buffer disable.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 155
FlexRay Module (FLEXRAYV2)
Table 3-92. Single Transmit Message Buffer Application Transitions
Transition HL HU Command MBCCSRn.LCKT:= 1 Condition Description
MBCCSRn.LCKS = 0 Application triggers message buffer lock. MBCCSRn.LCKS = 1 Application triggers message buffer unlock.
Module Transitions The module transitions that can be triggered by the FlexRay module are described in Table 3-93. Each transition will be triggered for certain message buffers when the related condition is fulfilled.
Table 3-93. Single Transmit Message Buffer Module Transitions
Transition SA MA TX SU STS Condition slot match and static slot slot match and CycleCounter match slot start and MBCCSRn.CMT = `1' status updated static slot start dynamic slot start or symbol window start or NIT start slot start or symbol window start or NIT start Description Slot Assigned - Message buffer is assigned to next static slot. Message Available - Message buffer is assigned to next slot and cycle counter filter matches. Transmission Slot Start - Slot Start and commit bit CMT is set. In case of a dynamic slot, pLatestTx is not exceeded. Status Updated - Slot Status field and message buffer status flags updated. Interrupt flag set. Static Slot Start - Start of static slot. Dynamic Slot or Segment Start. - Start of dynamic slot or symbol window or NIT. Slot or Segment Start - Start of static slot or dynamic slot or symbol window or NIT.
DSS
SSS
Transition Priorities The application can trigger only one transition at a time. There is no need to specify priorities among them. As shown in the first part of Table 3-94, the module transitions have a higher priority than the application transitions. For all states except the CCMa state, both a lock/unlock transition HL/HD and a module transition can be executed at the same time. The result state is reached by first applying the application transition and subsequently the module transition to the intermediately reached state. For example, if the message buffer is in the HLck state and the application unlocks the message buffer by the HU transition and the module triggers the slot assigned transition SA, the intermediate state is Idle and the resulting state is CCSa. The priorities among the module transitions is given in the second part of Table 3-94.
Table 3-94. Single Transmit Message Buffer Transition Priorities
State Idle, HLck CCMa Priorities SA > HD MA > HD TX > HL Description module vs. application Slot Assigned > Message Buffer Disable Message Available > Message Buffer Disable Transmission Start > Message Buffer Lock MFR4300 Data Sheet, Rev. 3 156 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-94. Single Transmit Message Buffer Transition Priorities
State Idle, HLck CCMa Priorities module internal MA > SA TX > STS TX > DSS Message Available > Slot Assigned Transmission Slot Start > Static Slot Start Transmission Slot Start > Dynamic Slot Start Description
3.4.6.2.4
Transmit Message Setup
To transmit a message over the FlexRay bus, the application writes the message data into the message buffer data field and sets the commit bit CMT in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). The physical access to the message buffer data field is described in Section 3.4.3.1, "Individual Message Buffers". As indicated by Table 3-91, the application shall write to the message buffer data field and change the commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or HLckCCMa. A message buffer can be identified for message transmission only if it is the Idle state. The application can change the state of a message buffer if it issues the appropriate commands given in Table 3-92. The state change is indicated through the MBCCSRn.EDS and MBCCSRn.LCKS status bits. If the transmit message buffer enters one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or HLckCCMa the MBCCSRn.DVAL flag is negated. 3.4.6.2.5 Message Transmission
As a result of the message buffer search described in Section 3.4.7, "Individual Message Buffer Search", the FlexRay module triggers the message available transition MA for up to two transmit message buffers. This changes the message buffer state from Idle to CCMa and the message buffers can be used for message transmission in the next slot. The FlexRay module transmits a message from a message buffer if both of the following two conditions are fulfilled at the start of the transmission slot: 1. the message buffer is in the message available state CCMa 2. the message data are still valid, i.e. MBCCSRn.CMT = `1' In this case, the FlexRay module triggers the TX transition and changes the message buffer state to CCTx. A transmit message buffer timing and state change diagram for message transmission is given in Figure 3-112. In this example, the message buffer with message buffer number n is Idle at the start of the search slot, matches the slot and cycle number of the next slot, and message buffer data are valid, i.e. MBCCSRn.CMT = `1'.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 157
FlexRay Module (FLEXRAYV2)
MA Idle
sta rt sta rt
TX CCMa
slot start
SSS SU CCTx
message transmit slot s+1
CCSu
slot start
MT sta rt
Idle
slot start
MT
search[s+1] slot s
MT
slot s+2
Figure 3-112. Message Transmission Timing
MA HLck
slot start
MT
HU HLckCCMa CCMa
sta rt
TX CCTx
slot start
SSS Idle
slot start
MT sta rt
sta rt
search[s+1] slot s
MT
message transmit slot s+1
slot s+2
Figure 3-113. Message Transmission from HLck state with unlock
The amount of message data read from the FRM and transferred to the FlexRay bus is determined by the following three items 1. the message buffer segment that the message buffer is assigned to, as defined by the Message Buffer Segment Size and Utilization Register (MBSSUTR). 2. the message buffer data field size, as defined by the related field of the Message Buffer Data Size Register (MBDSR) 3. the value of the PLDLEN field in the message buffer header field, as described in Section 3.4.5.2.1, "Frame Header Section Description" If a message buffer is assigned to message buffer segment 1, and PLDLEN > MBSEG1DS, then 2 * MBSEG1DS bytes will be read from the message buffer data field and zero padding is used for the remaining bytes for the FlexRay bus transfer. If PLDLEN <= MBSEG1DS, the FlexRay module reads and transfers 2*PLDLEN bytes. The same holds for segment 2 and MBSEG2DS. 3.4.6.2.6 Null Frame Transmission
A static slot with slot number S is assigned to the FlexRay module for channel A, if at least one transmit message buffer is configured with the MBFIDRn.FID set to S and MBCCFRn.CHA set to `1'. A Null Frame is transmitted in the static slot S on channel A, if this slot is assigned to the FlexRay module for channel A, and all transmit message buffers with MBFIDRn.FID = s and MBCCFRn.CHA = `1' are either not committed, i.e MBCCSRn.CMT = `0', or locked by the application, i.e. MBCCSRn.LCKS = `1', or the cycle counter filter is enabled and does not match. Additionally, the application can clear the commit bit of a message buffer that is in the CCMa state, which is called uncommit or transmit abort. This message buffer will be used for null frame transmission. As a result of the message buffer search described in Section 3.4.7, "Individual Message Buffer Search", the FlexRay module triggers the slot assigned transition SA for up to two transmit message buffers if at
MFR4300 Data Sheet, Rev. 3 158 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
least one of the conditions mentioned above is fulfilled for these message buffers. The transition SA changes the message buffer states from either Idle to CCSa or from HLck to HLckCCSa. In each case, these message buffers will be used for null frame transmission in the next slot. A message buffer timing and state change diagram for null frame transmission from Idle state is given in Figure 3-114. SA Idle
sta rt
STS CCSa
sta rt
SSS CCNf Idle
slot start
MT sta rt
slot start
slot start
MT
MT
search[s+1] slot s
null frame transmit slot s+1
slot s+2
Figure 3-114. Null Frame Transmission from Idle state
A message buffer timing and state change diagram for null frame transmission from HLck state is given in Figure 3-115. SA HLck
rt rt sta
STS HLckCCSa
sta
SSS HLckCCNf HLck
slot start
MT sta rt
slot start
search[s+1] slot s
slot start
MT
MT
null frame transmit slot s+1
slot s+2
Figure 3-115. Null Frame Transmission from HLck state
If a transmit message buffer is in the CCSa or HLckCCSa state at the start of the transmission slot, a null frame is transmitted in any case, even if the message buffer is unlocked or committed before the transmission slot starts. A transmit message buffer timing and state change diagram for null frame transmission for this case is given in Figure 3-116. SA HLck
slot start
sta MT
HU HLckCCSa CCSa
rt
STS CCNf
slot start
SSS Idle
slot start
MT sta rt
rt
search[s+1] slot s
MT
sta
null frame transmit slot s+1
slot s+2
Figure 3-116. Null Frame Transmission from HLck state with unlock
Since the null frame transmission will not use the message buffer data, the application can lock/unlock the message buffer during null frame transmission. A transmit message buffer timing and state change diagram for null frame transmission for this case is given in Figure 3-117.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 159
FlexRay Module (FLEXRAYV2)
SA Idle
sta rt
ST CCSa CCNf
slot start
HL HLckCCNf
SS HLck
slot start
MT sta rt
slot start
sta rt MT
search[s+1] slot s
MT
null frame transmit slot s+1
slot s+2
Figure 3-117. Null Frame Transmission from with locking
3.4.6.2.7
Message Buffer Status Update
After the end of each slot, the PE generates the slot status vector. Depending on the this status, the transmitted frame type, and the amount of transmitted data, the message buffer status is updated. Message Buffer Status Update after Complete Message Transmission The term complete message transmission refers to the fact that all payload data stored in the message buffer were send to FlexRay bus. In this case, the FlexRay module updates the slot status field of the message buffer and triggers the status updated transition SU. With the SU transition, the FlexRay module sets the message buffer interrupt flag MBCCSn.MBIF to indicate the successful message transmission. Depending on the transmission mode flag MBCCFRn.MTM, the FlexRay module changes the commit flag MBCCSRn.CMT and the valid flag MBCCSRn.DVAL. If the MBCCFRn.MTM flag is negated, the message buffer is in the event transmission mode. In this case, each committed message is transmitted only once. The commit flag MBCCSRn.CMT is cleared with the SU transition. If the MBCCFRn.MTM flag is asserted, the message buffer is in the state transmission mode. In this case, each committed message is transmitted as long as the application provides new data or locks the message buffers. The FlexRay module will not clear the MBCCSRn.CMT flag at the end of transmission and will set the valid flag MBCCSRn.DVAL to indicate that the message will be transmitted again. Message Buffer Status Update after Incomplete Message Transmission The term incomplete message transmission refers to the fact that not all payload data that should be transmitted were send to FlexRay bus. This may be caused by the following regular conditions in the dynamic segment: 1. The transmission slot starts in a minislot with a minislot number greater than pLatestTx. 2. The transmission slot did not exist in the dynamic segment at all. Additionally, an incomplete message transmission can be caused by internal communication errors. If those error occur, the Protocol Engine Communication Failure Interrupt Flag PECF_IF is set in the Protocol Interrupt Flag Register 1 (PIFR1). In any of these two cases, the status of the message buffer is not changed at all with the SU transition. The slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set.
MFR4300 Data Sheet, Rev. 3 160 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Message Buffer Status Update after Null Frame Transmission After the transmission of a null frame, the status of the message buffer that was used for the null frame transmission is not changed at all. The slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set.
3.4.6.3
Receive Message Buffers
The section provides a detailed description of the functionality of the receive message buffers. A receive message buffer is used to receive a message from the FlexRay Bus based on individual filter criteria. The FlexRay module uses the receive message buffer to provide the following data to the application 1. message data received 2. information about the reception process 3. status information about the slot in which the message was received A individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings * MBCCSRn.MBT = `0' (single buffered message buffer) * MBCCSRn.MTD = `0' (receive message buffer) To certain message buffer fields, both the application and the FlexRay module have access. To ensure data consistency, a message buffer locking scheme is implemented that is used to control the access to the data, control, and status bits of a message buffer. The access regions for receive message buffers are depicted in Figure 3-118. A description of the regions is given in Table 3-95. If an region is active as indicated in Table 3-96, the access scheme given for that region applies to the message buffer.
Message Buffer Header Field: Data Field Offset
CFG
Message Buffer Header Field: Frame Header Message Buffer Header Field: Slot Status
RX
MSG
Message Buffer Data Field: DATA[0-N] MBIDXRn.MBIDX MBCCSRn.DVAL/DUP MBCCSRn.MTD MBCCFRn.CHA/CHB/CCF* MBFIDRn.FID
SR
Figure 3-118. Receive Message Buffer Access Regions
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 161
FlexRay Module (FLEXRAYV2)
Table 3-95. Receive Message Buffer Access Region Description
Access from Region Application CFG MSG RX SR read/write read/write Module write-only read-only Message Buffer Configuration, Message Data and Status Access Message Data, Header, and Status Access Message Reception and Status Update Message Buffer Search Data Region used for
The trigger bits MBCCSRn.EDT and MBCCSRn.LCKT and the interrupt enable bit MBCCSRn.MBIE are not under access control and can be accessed from the application at any time. The status bits MBCCSRn.EDS and MBCCSRn.LCKS are not under access control and can be accessed from the FlexRay module at any time. The interrupt flag MBCCSRn.MBIF is not under access control and can be accessed from the application and the FlexRay module at any time. FlexRay module set access has higher priority. The FlexRay module restricts its access to the regions depending on the current state of the message buffer. The application must adhere to these restrictions in order to ensure data consistency. The receive message buffer states are given in Figure 3-119. A description of the message buffer states is given in Table 3-91, which also provides the access scheme for the access regions. The status bits MBCCSRn.EDS and MBCCSRn.LCKS provide the application with the required status information. The internal status information is not visible to the application.
RESET_STATE
HD HE HL SU
HDis
HL HU
Idle
BS SNS
CCSu
SSS SLS
HDisLck
HE
CCBs
HL HU
CCRx
HL HU
HD
HU BS
HLck
SNS
HLckCCBs
SLS
HLckCCRx
SSS
Figure 3-119. Receive Message Buffer States Table 3-96. Receive Message Buffer States and Access (Sheet 1 of 2)
MBCCSRn State EDS Idle HDis 1 0 LCKS 0 0 Appl. - CFG Module SR - Idle - Message Buffer is idle. Included in message buffer search. Disabled - Message Buffer under configuration. Excluded from message buffer search. Access from Description
MFR4300 Data Sheet, Rev. 3 162 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-96. Receive Message Buffer States and Access (Sheet 2 of 2)
MBCCSRn State EDS HDisLck HLck CCBs HLckCCBs CCRx HLckCCRx 0 1 1 1 1 1 LCKS 1 1 0 1 0 1 Appl. CFG MSG - MSG - MSG Module - - - - - - Disabled and Locked - Message Buffer under configuration. Excluded from message buffer search. Locked - Applications access to data, control, and status. Included in message buffer search. Buffer Subscribed - Message buffer subscribed for reception. Filter matches next (slot, cycle, channel) tuple. Locked and Buffer Subscribed - Applications access to data, control, and status. Message buffer subscribed for reception. Message Receive - Message data received into related shadow buffer. Locked and Message Receive - Applications access to data, control, and status. Message data received into related shadow buffer. Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. Access from Description
CCSu
1
0
-
RX
3.4.6.3.1
Message Buffer Transitions
Application Transitions The application transitions that can be triggered by the application using the commands described in Table 3-97. The application issues the commands by writing to the Message Buffer Configuration, Control, Status Registers (MBCCSRn). Only one command can be issued with one write access. Each command is executed immediately. If the command is ignored, it must be issued again. The enable and disable commands issued by writing `1' to the trigger bit MBCCSRn.EDT. The transition that will be triggered by each of these command depends on the current value of the status bit MBCCSRn.EDS. If the command triggers the disable transition HD and the message buffer is in one of the states CCBs, HLckCCBs, or CCRx, the disable transition has no effect (command is ignored) and the message buffer state is not changed. No notification is given to the application. The lock and unlock commands issued by writing `1' to the trigger bit MBCCSRn.LCKT. The transition that will be triggered by each of these commands depends on the current value of the status bit MBCCSRn.LCKS. If the command triggers the lock transition HL while the message buffer is in the state CCRx, the lock transition has no effect (command is ignored) and message buffer state is not changed. In this case, the message buffer lock error flag LCK_EF in the CHI Error Flag Register (CHIERFR) is set.
Table 3-97. Receive Message Buffer Application Transitions
Transition HE HD HL HU Host Command MBCCSRn.EDT:= 1 MBCCSRn.LCKT:= 1 Condition Description
MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDS = 1 Application triggers message buffer disable. MBCCSRn.LCKS = 0 Application triggers message buffer lock. MBCCSRn.LCKS = 1 Application triggers message buffer unlock.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 163
FlexRay Module (FLEXRAYV2)
Module Transitions The module transitions that can be triggered by the FlexRay module are described in Table 3-98. Each transition will be triggered for certain message buffers when the related condition is fulfilled.
Table 3-98. Receive Message Buffer Module Transitions
Transition BS SLS SNS SSS Condition slot match and CycleCounter match slot start symbol window start or NIT start slot start or symbol window start or NIT start status updated Description Buffer Subscribed - The message buffer filter matches next slot and cycle. Slot Start - Start of either Static Slot or Dynamic Slot. Symbol Window or NIT Start - Start of either Symbol Window or NIT. Slot or Segment Start - Start of either Static Slot, Dynamic Slot, Symbol Window, or NIT. Status Updated - Slot Status field, message buffer status flags, header index updated. Interrupt flag set.
SU
Transition Priorities The application can trigger only one transition at a time. There is no need to specify priorities among them. As shown in Table 3-99, the module transitions have a higher priority than the application transitions. For all states except the CCRx state, a module transition and the application lock/unlock transition HL/HU and can be executed at the same time. The result state is reached by first applying the module transition and subsequently the application transition to the intermediately reached state. For example, if the message buffer is in the buffer subscribed state CCBs and the module triggers the slot start transition SLS at the same time as the application locks the message buffer by the HL transition, the intermediate state is CCRx and the resulting state is locked buffer subscribed state HLckCCRx.
Table 3-99. Receive Message Buffer Transition Priorities
State Idle HLck CCRx Priorities BS > HD BS > HD SSS > HL Description module vs. application Buffer Subscribed > Message Buffer Disable Buffer Subscribed > Message Buffer Disable Slot or Segment Start > Message Buffer Lock
3.4.6.3.2
Message Buffer Search
The FlexRay module starts a sequential search that checks all message buffers at the following protocol related events: * slot start, in the static frame segment * minislot start, in the dynamic frame segment * NIT start The filters that are used for the search are described in Section 3.4.7.1, "Individual Message Buffer Filtering".
MFR4300 Data Sheet, Rev. 3 164 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
As a result of the message buffer search, the FlexRay module changes the state of up to two enabled receive message buffers from either idle state Idle or locked state HLck to the either subscribed state CCBs or locked buffer subscribed state HLckCCBs by triggering the buffer subscribed transition BS. If the receive message buffers for the next slot are assigned to both channels, then at most one receive message buffer is changed to a buffer subscribed state. If more than one matching message buffers assigned to a certain channel, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. 3.4.6.3.3 Message Reception
With the start of the next static or dynamic slot the module trigger the slot start transition SLS. This changes the state of the subscribed receive message buffers from either CCBs to CCRx or from HLckCCBs to HLckCCRx, respectively. During the reception slot, the received frame data are written into the shadow buffers. For details on receive shadow buffers, see Section 3.4.6.3.6, "Receive Shadow Buffers Concept". The data and status of the receive message buffers that are the CCRx or HLckCCRx are not modified in the reception slot. 3.4.6.3.4 Message Buffer Status Update
With the start of the next static or dynamic slot or with the start of the symbol window or NIT, the module trigger the slot or segment start transition SSS. This transition changes the state of the receiving receive message buffers from either CCRx to CCSu or from HLckCCRx to HLck, respectively. If a message buffer was in the locked state HLckCCRx, no update will be performed. The received data are lost. This is indicated by setting the Frame Lost Channel A/B Error Flag FRLA_EF/FRLB_EF in the CHI Error Flag Register (CHIERFR). If a message buffer was in the CCRx state it is now in the CCSu state. After the evaluation of the slot status provided by the PE the message buffer is updated. The message buffer update depends on the slot status bits and the segment the message buffer is assigned to. This is described in Table 3-100.
Table 3-100. Receive Message Buffer Update
vSS!ValidFrame 1 vRF!Header!NFIndicator 1 Update description Valid non-null frame received. - Message Buffer Data Field updated. - Frame Header Field updated. - Slot Status Field updated. - DUP:= 1 - DVAL:= 1 - MBIF:= 1 Valid null frame received. - Message Buffer Data Field not updated. - Frame Header Field not updated. - Slot Status Field updated. - DUP:= 0 - DVAL not changed - MBIF:= 1
1
0
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 165
FlexRay Module (FLEXRAYV2)
Table 3-100. Receive Message Buffer Update (Continued)
vSS!ValidFrame 0 vRF!Header!NFIndicator x Update description No valid frame received. - Message Buffer Data Field not updated. - Frame Header Field not updated. - Slot Status Field updated. - DUP:= 0 - DVAL not changed. - MBIF:= 1, if the slot was not an empty dynamic slot. Note: An empty dynamic slot is indicated by the following frame and slot status bit values: vSS!ValidFrame = 0 and vSS!SyntaxError = 0 and vSS!ContentError = 0 and vSS!BViolation = 0.
NOTE If the number of the last slot in the current communication cycle on a given channel is n, then all receive message buffers assigned to this channel with MBFIDRn.FID > n will not be updated at all. When the receive message buffer update has finished the status updated transition SU is triggered, which changes the buffer state from CCSu to Idle. An example receive message buffer timing and state change diagram for a normal frame reception is given in Figure 3-120. BS Idle
s ta rt s ta rt
SLS CCBs
slot start
SSS SU CCRx
message receive to receive shadow buffer slot s+1
CCSu
slot start
MT sta rt
Idle
slot start
MT
search[s+1] slot s
MT
slot s+2
Figure 3-120. Message Reception Timing
The amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: 1. the message buffer segment that the message buffer is assigned to, as defined by the Message Buffer Segment Size and Utilization Register (MBSSUTR). 2. the message buffer data field size, as defined by the related field of the Message Buffer Data Size Register (MBDSR) 3. the number of bytes received over the FlexRay bus If the message buffer is assigned to the message buffer segment 1, and the number of received bytes is greater than 2*MBDSR.MBSEG1DS, the FlexRay module writes only 2*MBDSR.MBSEG1DS bytes into the message buffer data field of the receive shadow buffer. If the number of received bytes is less than 2*MBDSR.MBSEG1DS, the FlexRay module writes only the received number of bytes and will not change the trailing bytes in the message buffer data field of the receive shadow buffer. The same holds for the message buffer segment 2 with MBDSR.MBSEG2DS.
MFR4300 Data Sheet, Rev. 3 166 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.4.6.3.5
Received Message Access
To access the message data received over the FlexRay bus, the application reads the message data stored in the message buffer data field of the corresponding receive message buffer. The access to the message buffer data field is described in Section 3.4.3.1, "Individual Message Buffers". The application can read the message buffer data field if the receive message buffer is one of the states HDis, HDisLck, or HLck. If the message buffer is in one of these states, the FlexRay module will not change the content of the message buffer. 3.4.6.3.6 Receive Shadow Buffers Concept
The receive shadow buffer concept applies only to individual receive message buffers. The intention of this concept is to ensure that only syntactically and semantically valid received non-null frames are presented to the application in a receive message buffer. The basic structure of a receive shadow buffer is described in Section 3.4.3.2, "Receive Shadow Buffers". The receive shadow buffers temporarily store the received frame header and message data. After the slot boundary the slot status information is generated. If the slot status information indicates the reception of the valid non-null frame (see Table 3-100), the FlexRay module writes the slot status into the slot status field of the receive shadow buffer and exchanges the content of the Message Buffer Index Registers (MBIDXRn) with the content of the corresponding internal shadow buffer index register. In all other cases, the FlexRay module writes the slot status into the identified receive message buffer, depending on the slot status and the FlexRay segment the message buffer is assigned to. The shadow buffer concept, with its index exchange, results in the fact that the FRM located message buffer associated to an individual receive message buffer changes after successful reception of a valid frame. This means that the message buffer area in the FRM accessed by the application for reading the received message is different from the initial setting of the message buffer. Therefore, the application must not rely on the index information written initially into the Message Buffer Index Registers (MBIDXRn). Instead, the index of the message buffer header field must be fetched from the Message Buffer Index Registers (MBIDXRn).
3.4.6.4
Double Transmit Message Buffer
The section provides a detailed description of the functionality of the double transmit message buffers. Double transmit message buffers are used by the application to provide the FlexRay module with the message data to be transmitted over the FlexRay Bus. The FlexRay module uses this message buffer to provide information to the application about the transmission process, and status information about the slot in which message data was transmitted. In contrast to the single transmit message buffers, the application can provide new transmission data while the transmission of the previously provided message data is running. This scheme is called double buffering and can be considered as a FIFO of depth 2. Double transmit message buffers are implemented by combining two individual message buffers that form the two sides of an double transmit message buffer. One side is called the commit side and will be accessed by the application to provide the message data. The other side is called the transmit side and is used by the
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 167
FlexRay Module (FLEXRAYV2)
FlexRay module to transmit the message data to the FlexRay bus. The two sides are located in adjacent individual message buffers. The message buffer that implements the commit side has an even message buffer number 2n. The transmit side message buffer follows the commit side message buffer and has the message buffer number 2n+1. The basic structure and data flow of a double transmit message buffer is given in Figure 3-121.
Application
message data Internal Message Transfer message data
FlexRay Bus MB# 2n+1 Transmit Side
message data
MB# 2n Commit Side
Figure 3-121. Double Transmit Buffer Structure and Data Flow
NOTE Both the commit and the transmit side must be configured with identical values except for the Message Buffer Index Registers (MBIDXRn). 3.4.6.4.1 Access Regions
To certain message buffer fields, both the application and the FlexRay module have access. To ensure data consistency, a message buffer locking scheme is implemented, which controls the exclusive access to the data, control, and status bits of the message buffer. The access scheme for double transmit message buffers is depicted in Figure 3-122. The given regions represent fields that can be accessed from both the application and the FlexRay module and, thus, require access restrictions. A description of the regions is given in Table 3-101.
Commit Side
Message Buffer Header Field: Frame Header
CFG
Transmit Side
Message Buffer Header Field: Frame Header
CFG
Message Buffer Header Field: Data Field Offset MBIDXR[2n].MBIDX MBCCSR[2n]n.CMT
ITX
Message Buffer Header Field: Data Field Offset MBIDXR[2n+1].MBIDX MBCCSR[2n+1].CMT Message Buffer Data Field: DATA[0-N]
TX
MSG
Message Buffer Data Field: DATA[0-N] Message Buffer Header Field: Slot Status MBCCSR[2n].MBT/MTD MBCCFR[2n].MTM/CHA/CHB/CCF* MBFIDR[2n].FID
SS
Message Buffer Header Field: Slot Status MBCCSR[2n+1].MBT/MTD MBCCFR[2n+1].MTM/CHA/CHB/CCF* MBFIDR[2n+1].FID
SS
SR
Figure 3-122. Double Transmit Message Buffer Access Regions Layout
MFR4300 Data Sheet, Rev. 3 168 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-101. Double Transmit Message Buffer Access Regions Description
Access Type Region Application CFG MSG ITX SS CFG SR TX SS read/write read/write read/write Module Commit Side read/write write-only read-only read-only write-only Message Buffer Configuration Message Buffer Data and Control access Internal Message Transfer. Slot Status Update Transmit Side Message Buffer Configuration Message Buffer Search Internal Message Transfer, Message Transmission Slot Status Update Description
The trigger bits MBCCSRn.EDT and MBCCSRn.LCKT, and the interrupt enable bit MBCCSRn.MBIE are not under access control and can be accessed from the application at any time. The status bits MBCCSRn.EDS and MBCCSRn.LCKS are not under access control and can be accessed from the FlexRay module at any time. The interrupt flag MBCCSnR.MBIF is not under access control and can be accessed from the application and the FlexRay module at any time. FlexRay module set access has higher priority. The FlexRay module restricts its access to the regions, depending on the current state of the corresponding part of the double transmit message buffer. The application must adhere to these restrictions in order to ensure data consistency. The states for the commit side of a double transmit message buffer are given in Figure 3-123. A description of the states is given in Table 3-103. The states for the transmit side of a double transmit message buffer are given in Figure 3-124. A description of the states is given in Table 3-103. The description tables also provide the access scheme for the access regions. The status bits MBCCSRn.EDS and MBCCSRn.LCKS provide the application with the required message buffer status information. The internal status information is not visible to the application. 3.4.6.4.2 Message Buffer States
This section describes the transmit message buffer states and provides a state diagram.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 169
FlexRay Module (FLEXRAYV2)
RESET_STATE
HDis
HL HU
HD HE HL IS
Idle
IE
HDisLck
HE HD
CCITx
HU
HLck Figure 3-123. Double Transmit Message Buffer State Diagram (Commit Side)
A description of the states of the commit side of a double transmit message buffer is given in Table 3-102.
Table 3-102. Double Transmit Message Buffer State Description (Commit Side)
MBCCSR[2n] State EDS common states HDis CCITx 0 1 0 0 CFG - - ITX Disabled - Message Buffer under configuration. Commit Side can not be used for internal message transfer. Internal Message Transfer - Message Buffer Data transferred from commit side to transmit side. Idle - Message Buffer Commit Side is idle. Commit Side can be used for internal message transfer. Disabled and Locked - Message Buffer under configuration. Commit Side can not be used for internal message transfer. Locked - Applications access to data, control, and status. Commit Side can not be used for internal message transfer. LCKS Appl. Module Access Region Description
commit side specific states Idle HDisLck HLck 1 0 1 0 1 1 - CFG SS MSG SS ITX, SS
MFR4300 Data Sheet, Rev. 3 170 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
RESET_STATE
HDis
HD HE IS
Idle
SA MA
SU
CCSu
DSS
SSS
CCSa
IS STS DSS STS
CCTx
IE
IE
SSS
TX
CCITx
CCSaCCITx
CCNf
IS IE
CCMa
IS IE
CCNfCCITx
CCMaCCITx
Figure 3-124. Double Transmit Message Buffer State Diagram (Transmit Side)
A description of the states of the transmit side of a double transmit message buffer is given in Table 3-103.
Table 3-103. Double Transmit Message Buffer State Description (Transmit Side) (Sheet 1 of 2)
MBCCSRn State EDS common states HDis CCITx 0 1 0 0 CFG - - TX Disabled - Message Buffer under configuration. Excluded from message buffer search. Internal Message Transfer - Message Buffer Data transferred from commit side to transmit side. Idle - Message Buffer Transmit Side is idle. Transmit Side is included in message buffer search. Slot Assigned - Message buffer assigned to next static slot. Ready for Null Frame transmission. Slot Assigned and Internal Message Transfer - Message buffer assigned to next static slot and Message Buffer Data transferred from commit side to transmit side. Null Frame Transmission Header is used for null frame transmission. Null Frame Transmission and Internal Message Transfer Header is used for null frame transmission and Message Buffer Data transferred from commit side to transmit side. Message Available - Message buffer is assigned to next slot and cycle counter filter matches. Message Available and Internal Message Transfer - Message buffer is assigned to next slot and cycle counter filter matches and Message Buffer Data transferred from commit side to transmit side. Message Transmission - Message buffer data transmit. Payload data from buffer transmitted LCKS Appl. Module Access Region Description
transmit side specific states Idle CCSa CCSaCCITx 1 1 1 0 0 0 - - - SR - TX
CCNf CCNfCCITx
1 1
0 0
- -
TX TX
CCMa CCMaCCITx
1 1
0 0
- -
- -
CCTx
1
0
-
TX
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 171
FlexRay Module (FLEXRAYV2)
Table 3-103. Double Transmit Message Buffer State Description (Transmit Side) (Sheet 2 of 2)
MBCCSRn State EDS CCSu 1 LCKS 0 Appl. - Module SS Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. Note: The slot status field of the commit side is updated too, even if the application has locked the commit side. Access Region Description
3.4.6.4.3
Message Buffer Transitions
Application Transitions The application transitions that can be triggered by the application using the commands described in Table 3-104. The application issues the commands by writing to the Message Buffer Configuration, Control, Status Registers (MBCCSRn). Only one command can be issued with one write access. Each command is executed immediately. If the command is ignored, it must be issued again. The enable and disable commands can be issued on the transmit side only. Any enable or disable command issued on the commit side will be ignored without notification. The transitions that will be triggered depends on the value of the EDS bit. The enable and disable commands will affect both the commit side and the transmit side at the same time. If the application triggers the disable transition HD while the transmit side is in one of the states CCSa, CCSaCCITx, CCNf, CCNfCCITx, CCMa, CCMaCCITx, CCTx, or CCSu, the disable transition has no effect (command is ignored) and the message buffer state is not changed. No notification is given to the application. The lock and unlock commands can be issued on the commit side only. Any lock or unlock command issued on the transmit side will be ignored and the double transmit buffer lock error flag DBL_EF in the CHI Error Flag Register (CHIERFR) will be set. The transitions that will be triggered depends on the current value of the LCKS bit. The lock and unlock commands will only affect the commit side. If the application triggers the lock transition HL while the commit side is in the state CCITx, the message buffer state will not be changed and the message buffer lock error flag LCK_EF in the CHI Error Flag Register (CHIERFR) will be set.
Table 3-104. Double Transmit Message Buffer Host Transitions
Transition HE HD HL HU Host Command MBCCSR[2n+1].EDT:= 1 MBCCSR[2n].LCKT:= 1 Condition Description
MBCCSR[2n+1].EDS = 0 Application triggers message buffer enable. MBCCSR[2n+1].EDS = 1 Application triggers message buffer disable. MBCCSR[2n].LCKS = 0 Application triggers message buffer lock. MBCCSR[2n].LCKS = 1 Application triggers message buffer unlock.
Module Transitions The module transitions that can be triggered by the FlexRay module are described in Table 3-105. The transitions C1 and C2 apply to both sides of the message buffer and are applied at the same time. All other FlexRay module transitions apply to the transmit side only.
MFR4300 Data Sheet, Rev. 3 172 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-105. Double Transmit Message Buffer Module Transitions
Transition common transitions IS IE see Section 3.4.6.4.5, "Internal Message Transfer Internal Message Transfer Start - Start transfer of message data from commit side to transmit side. Internal Message Transfer End - Stop transfer of message data from commit side to transmit side. Note: The internal message transfer is stopped before the slot or segment start. Slot Assigned - Message buffer is assigned to next static slot. Message Available - Message buffer is assigned to next slot and cycle counter filter matches. Condition Description
transmit side specific transitions SA MA TX SU STS slot match and static slot slot match and CycleCounter match
slot start and Transmission Slot Start - Slot Start and commit bit CMT is set. MBCCSR[2n+1].CMT = 1 In case of a dynamic slot, pLatestTx is not exceeded. status updated static slot start dynamic slot start or symbol window start or NIT start slot start or symbol window start or NIT start Status Updated - Slot Status field and message buffer status flags updated. Interrupt flag set. Static Slot Start - Start of static slot. Dynamic Slot or Segment Start. - Start of dynamic slot or symbol window or NIT. Slot or Segment Start - Start of static slot or dynamic slot or symbol window or NIT.
DSS
SSS
Transition Priorities The application can trigger only one transition at a time. There is no need to specify priorities among them. As shown in the first part of Table 3-106, the module transitions have a higher priority than the application transitions. The priorities among the FlexRay module transitions and the related states are given in the second part of Table 3-106. These priorities apply only to the transmit side. The internal message transmit start transition IS has tho lowest priority.
Table 3-106. Double Transmit Message Buffer Transition Priorities
State Idle Priority IS > HD IS > HL MA > SA TX > STS TX > DSS Description module vs. application Internal Message Transfer Start > Message Buffer Disable Internal Message Transfer Start > Message Buffer Lock module internal Idle CCMa Message Available > Slot Assigned Transmission Slot Start > Static Slot Start Transmission Slot Start > Dynamic Slot Start
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 173
FlexRay Module (FLEXRAYV2)
3.4.6.4.4
Message Preparation
The application provides the message data through the commit side. The transmission itself is executed from the transmit side. The transfer of the message data from the commit side to the transmit side is done by the Internal Message Transfer, which is described in Section 3.4.6.4.5, "Internal Message Transfer To transmit a message over the FlexRay bus, the application writes the message data into the message buffer data field of the commit side and sets the commit bit CMT in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). The physical access to the message buffer data field is described in Section 3.4.3.1, "Individual Message Buffers". As indicated by Table 3-102, the application shall write to the message buffer data field and change the commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, or HLck. The application can change the state of a message buffer if it issues the appropriate commands given in Table 3-104. The state change is indicated through the MBCCSRn.EDS and MBCCSRn.LCKS status bits. 3.4.6.4.5 Internal Message Transfer
The internal message transfer transfers the message data from the commit side to the transmit side. The internal message transfer is implemented as the swapping of the content of the Message Buffer Index Registers (MBIDXRn) of the commit side and the transmit side. After the swapping, the commit side CMT bit is cleared, the commit side interrupt flag MBIF is set, the transmit side CMT bit is set, and the transmit side DVAL bit is cleared. The conditions and the point in time when the internal message transfer is started are controlled by the message buffer commit mode bit MCM in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). The MCM bit configures the message buffer for either the streaming commit mode or the immediate commit mode. A detailed description is given in Streaming Commit Mode and Immediate Commit Mode. The Internal Message Transfer is triggered with the transition IS. Both sides of the message buffer enter enter one of the CCITx states. The internal message transfer is finished with the transition IE. Streaming Commit Mode The intention of the streaming commit mode is to ensure that each committed message is transmitted at least once. The FlexRay module will not start the Internal Message Transfer for a message buffer as long as the message data on the transmit side is not transmitted at least once. The streaming commit mode is configured by clearing the message buffer commit mode bit MCM in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). In this mode, the internal message transfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the Idle state 2. the commit site message data are valid, i.e. MBCCSR[2n].CMT = 1 3. the transmit side is in one of the states Idle, CCSa, or CCMa 4. the transmit side contains either no valid message data, i.e. MBCCSR[2n+1].CMT = 0 or the message data were transmitted at least once, i.e. MBCCSR[2n+1].DVAL = 1
MFR4300 Data Sheet, Rev. 3 174 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
An example of a streaming commit mode state change diagram is given in Figure 3-125. In this example, both the commit and the transmit side do not contain valid message data and the application provides two messages. The message buffer does not match the next slot. HL
Commit Side
HU HLck Idle Idle
IS CCITx CCITx
IE Idle
HL HLck
HU Idle
no internal message transfer, until message transmitted
Idle
Transmit Side
Idle
slot start slot start slot s+1
slot start
search[s+1] slot s
slot s+2
Figure 3-125. Internal Message Transfer in Streaming Commit Mode
Immediate Commit Mode The intention of the immediate commit mode is to transmit the latest data provided by the application. This implies that it is not guaranteed that each provided message will be transmitted at least once. The immediate commit mode is configured by setting the message buffer commit mode bit MCM in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). In this mode, the internal message transfer from the commit side to the transmit side is started for one double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the Idle state 2. the commit site message data are valid, i.e. MBCCSR[2n].CMT = 1 3. the transmit side is in one of the states Idle, CCSa, or CCMa It is not checked whether the transmit side contains no valid message data or valid message data were transmitted at least once. If message data are valid and not transmitted, they may be overwritten. An example of a streaming commit mode state change diagram is given in Figure 3-126. In this example, both the commit and the transmit side do not contain valid message data, and the application provides two messages and the first message is gets overwritten. The message buffer does not match the next slot. HL
Commit Side
HU HLck Idle Idle
IS CCITx CCITx
IE Idle
HL HLck Idle
slot start
HU Idle
IS CCITx CCITx
IE Idle Idle
slot start
Idle
Transmit Side
internal message transfer overwrites non-transmitted message
slot start
search[s+1] slot s
slot s+1
slot s+2
Figure 3-126. Internal Message Transfer in Immediate Commit Mode
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 175
FlexRay Module (FLEXRAYV2)
3.4.6.4.6
Message Transmission
For double transmit message buffers, the message buffer search checks only the transmit side part. The internal scheduling ensures, that the internal message transfer is stopped on the message buffer search start. Thus, the transmit side of message buffer, that is not in its transmission or status update slot, is always in the Idle state. The message transmit behavior and transmission state changes of the transmit side of a double transmit message buffer are the same as for single buffered transmit buffers, except that the transmit side of double buffers can not be locked by the application, i.e. the HU and HL transition do not exist. Therefore, refer to Section 3.4.6.2.5, "Message Transmission" 3.4.6.4.7 Message Buffer Status Update
The message buffer status update behavior of the transmit side of a double transmit message buffer is the same as for single transmit message buffers which is described in Section 3.4.6.2.7, "Message Buffer Status Update". Additionally, the slot status field of the commit side is update after the update of the slot status field of the transmit side, even if the commit side is locked by the application. This is implemented to provide the slot status of the most recent transmission slot.
3.4.7
Individual Message Buffer Search
This section provides a detailed description of the message buffer search algorithm. The message buffer search checks all enabled individual message buffer to determine if a certain slot is assigned to this node for transmission or if this node is subscribed to a certain slot for reception. The message buffer search is a sequential algorithm and is started at the following protocol related events: * each NIT start * each slot start in the static frame segment * each minislot start in the dynamic frame segment The search within the NIT searches for message buffers assigned or subscribed to slot 1. The search within slot n searches for message buffers assigned or subscribed to slot n+1. If the message buffer search is running while the next message buffer search start event appears, the message buffer search is stopped and the Message Buffer Search Error Flag MSB_EF is set in the CHI Error Flag Register (CHIERFR). This appears only if the CHI frequency is to low to search through all message buffers within the NIT or a minislot. The message buffer result is not defined in this case. For more details see Section 3.5.2, "Number of Usable Message Buffers". The filters criteria used for the message buffer search described in Section 3.4.7.1, "Individual Message Buffer Filtering". For double transmit message buffers only the transmit side is included in the search. During the search, a list of all matching message buffers is created. If all message buffers assigned or subscribed to the next slot are assigned to only one channel, then two lists of matching message buffer will be created, one for each channel. If all message buffers assigned or subscribed to the next slot are assigned to both channels, only one sorted list of matching message buffers is created.
MFR4300 Data Sheet, Rev. 3 176 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Each message buffer list is sorted according to the priorities given in Table 3-107. From the group with the highest priority, the message buffer with the lowest message buffer number is selected. For this message buffer the corresponding transition given in Table 3-107 is triggered as the result of the message buffer search.
Table 3-107. Message Buffer Search Priority
MBCCSRn Priority MTD (highest) 0 1 2 3 (lowest) 4
1
Description LCKS 0 0 1 x 0 1 CMT 1 0 x x 0 1 CCFM1 1 1 1 0 1 1 transmit buffer, locked or uncommitted, matches cycle count transmit buffer, assigned to slot receive buffer, unlocked, matches cycle count receive buffer, locked, matches cycle count transmit buffer, unlocked, committed, matches cycle count
Transition
1 1 1 1 0 0
MA SA SA SA SB SB
Cycle Counter Filter Match, see Section 3.4.7.1.2, "Message Buffer Cycle Counter Filtering"
3.4.7.1
Individual Message Buffer Filtering
The message buffer search identifies the matching message buffers by applying two individual message buffer filter. The first filter is the frame ID filter, the second filter is the cycle count filter. 3.4.7.1.1 Message Buffer Frame ID Filtering
The message buffer frame ID filter is used to determine if the message buffer can be considered for reception or transmission in a certain slot on a per channel basis. The frame ID filter matches for a message buffer with message buffer number n and the search slot s, if the value of the FID field in the Message Buffer Frame ID Registers (MBFIDRn) equals s. Only message buffer with a frame ID filter match may appear in the matching message buffer list. All transmit message buffer with a matching frame ID will appear in the matching message buffer list. Only receive message buffer with a matching frame ID and a matching cycle counter filter will appear in the matching message buffer list. 3.4.7.1.2 Message Buffer Cycle Counter Filtering
The message buffer cycle counter filter is a value-mask filter defined by the CCFE, CCFMSK, and CCFVAL fields in the Message Buffer Cycle Counter Filter Registers (MBCCFRn). This filter determines a set of communication cycles in which the message buffer is considered for message reception or message transmission. If the cycle counter filter is disabled, i.e. CCFE = `0', this set of cycles consists of all communication cycles. If the cycle counter filter of a message buffer does not match a certain communication cycle number, this message buffer is not considered for message transmission or reception in that communication cycle. In case of a transmit message buffer, though, this buffer is added to the matching message buffer list with
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 177
FlexRay Module (FLEXRAYV2)
CCFM = `0' to indicate the slot assignment and to trigger the null frame transmission. In case of an receive message buffer, this buffer is not added to the matching message buffer list. A message buffer matches its cycle counter filter for the communication cycle with the number CCN if at least one of the following conditions evaluates to true:
MBCCFRn.CCFE == 0 CCN[5:0] & MBCCFRn.CCFMSK[5:0] == MBCCFRn.CCFVAL[5:0] & MBCCFRn.CCFMSK[5:0] Eqn. 3-8 Eqn. 3-9
3.4.7.1.3
Message Buffer Channel Assignment Consistency
The message buffer channel assignment given by the CHA and CHB bits in the Message Buffer Cycle Counter Filter Registers (MBCCFRn) defines the channels on which the message buffer will receive or transmit. The message buffer with number n transmits or receives on channel A if MBCCFRn.CHA = `1' and transmits or receives on channel B if MBCCFRn.CHB = `1'. To ensure correct message buffer operation, all message buffers assigned to the same slot must have a consistent channel assignment. That means that all message buffers assigned to the same slot must be either assigned to only one channel, or assigned to both channels. The behavior of the message buffer search is not defined, if both types of channel assignments occur for one slot. An inconsistent channel assignment for message buffer 0 and message buffer 1 is depicted in Figure 3-127.
MB0 MBFIDR0.FID = 10 MBFIDR1.FID = 10 MBCCFR0.CHA = 1, MBCCFR0.CHB = 0 MBCCFR1.CHA = 1, MBCCFR1.CHB = 1 single channel assignment dual channel assignment
MB1
Figure 3-127. Inconsistent Channel Assignment
3.4.8
Individual Message Buffer Reconfiguration
The initial configuration of each individual message buffer can be changed even when the protocol is not in the POC:config state. This is referred to as individual message buffer reconfiguration. The configuration bits and fields that can be changed are given in the section on Specific Configuration Data. The common configuration data given in the section on Specific Configuration Data can not be reconfigured when the protocol is out of the POC:config state.
3.4.8.1
Reconfiguration Schemes
Depending on the target and destination basic state of the message buffer that is to be reconfigured, there are three reconfiguration schemes. 3.4.8.1.1 Basic Type Not Changed (RC1)
A reconfiguration will not change the basic type of the individual message buffer, if both the message buffer transfer direction bit MBCCSn.MTD and the message buffer type bit MBCCSn.MBT are not changed. This type of reconfiguration is denoted by RC1 in Figure 3-128. Single transmit and receive
MFR4300 Data Sheet, Rev. 3 178 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
message buffers can be RC1-reconfigured when in the HDis or HDisLck state. Double transmit message buffers can be RC1-reconfigured if both the transmit side and the commit side are in the HDis state. 3.4.8.1.2 Buffer Type Not Changed (RC2)
A reconfiguration will not change the buffer type of the individual message buffer if the message buffer buffer type bit MBCCSRn.MBT is not changed. This type of reconfiguration is denoted by RC2 in Figure 3-128. It applies only to single transmit and receive message buffers. Single transmit and receive message buffers can be RC2-reconfigured when in the HDis or HDisLck state. 3.4.8.1.3 Buffer Type Changed (RC3)
A reconfiguration will change the buffer type of the individual message buffer if the message buffer type bit MBCCSRn.MBT is changed. This type of reconfiguration is denoted by RC3 in Figure 3-128. The RC3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into one double buffer. In the later case, the two single message buffers must have consecutive message buffer numbers and the smaller one must be even. Message Buffers can be RC3 reconfigured if they are in the HDis state.
RC2 RC1
RC1
single RX
RC3
single TX
RC3
double TX (commit side) double TX (transmit side)
RC1
Figure 3-128. Message Buffer Reconfiguration Scheme
3.4.9
Receive FIFO
This section provides a detailed description of the two receive FIFOs.
3.4.9.1
Overview
The receive FIFOs implement the queued receive buffer defined by the FlexRay Communications System Protocol Specification, Version 2.1. One receive FIFO is assigned to channel A, the other receive FIFO is assigned to channel B. Both FIFOs work completely independent from each other. The message buffer structure of each FIFO is described in Section 3.4.3.3, "Receive FIFO". The area in the FRM for each of the two receive FIFOs is characterized by: * The index of the first FIFO entry given by Receive FIFO Start Index Register (RFSIR) * The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth and Size Register (RFDSR)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 179
FlexRay Module (FLEXRAYV2)
3.4.9.2
Receive FIFO Configuration
The receive FIFO control and configuration data are given in Section 3.4.3.7, "Receive FIFO Control and Configuration Data". The configuration of the receive FIFOs consists of two steps. The first step is the allocation of the required amount of FRM for the FlexRay window. This includes the allocation of the message buffer header area and the allocation of the message buffer data fields. For more details see Section 3.4.4, "FlexRay Memory Layout". The second step is the programming of the configuration data register while the PE is in POC:config. The following steps configure the layout of the FIFO. * The number of the first message buffer header index that belongs to the FIFO is written into the Receive FIFO Start Index Register (RFSIR). * The depth of the FIFO is written into the FIFO_DEPTH field in the Receive FIFO Depth and Size Register (RFDSR). * The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in the Receive FIFO Depth and Size Register (RFDSR). NOTE To ensure, that the read index RDIDX always points to a message buffer that contains valid data, the receive FIFO must have at least 2 entries. The FIFO filters are configured through the fifo filter registers.
3.4.9.3
Receive FIFO Reception
The frame reception to the receive FIFO is enabled, if for a certain slots no message buffer is assigned or subscribed. In this case the FIFO filter path shown in Figure 3-129 is activated. When the receive FIFO filter path indicates that the received frame must be appended to the FIFO, the FlexRay module writes the received frame header and slot status into the message buffer header field indicated by the internal FIFO header write index. The payload data are written in the message buffer data field. If the status of the received frame indicates a valid frame, the internal FIFO header write index is updated and the fifo not-empty interrupt flag FNEAIF/FNEBIF in the Global Interrupt Flag and Enable Register (GIFER) is set.
3.4.9.4
Receive FIFO Message Access
If the fifo not-empty interrupt flag FNEAIF/FNEBIF in the Global Interrupt Flag and Enable Register (GIFER) is set, the receive FIFO contains valid received messages, which can be accessed by the application. The receive FIFO does not require locking to access the message buffers. To access the message the application first reads the receive FIFO read index RDIDX from the Receive FIFO A Read Index Register (RFARIR) or Receive FIFO B Read Index Register (RFBRIR), respectively. This index points to the message buffer header field of the next message buffer that contains valid data. The application can access the message data as described in Section 3.4.3.3, "Receive FIFO". When the application has read all message buffer data and status information, it writes `1' to the fifo not-empty interrupt flags FNEAIF or
MFR4300 Data Sheet, Rev. 3 180 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
FNEBIF. This clears the interrupt flag and updates the RDIDX field in the Receive FIFO A Read Index Register (RFARIR) or Receive FIFO B Read Index Register (RFBRIR), respectively.When the RDIDX value has reached the last message buffer header field that belongs to the fifo, it wraps around to the index of the first message buffer header field that belongs to the fifo. This value is provided by the SIDX field in the Receive FIFO Start Index Register (RFSIR).
3.4.9.5
Receive FIFO filtering
The receive FIFO filtering is activated after all enabled individual receive message buffers have been searched without success for a message buffer to receive the current frame.
The FlexRay module provides three sets of FIFO filters. The FIFO filters are applied to valid non-null frames only. The FIFO will not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified in the related section given below. Only frames that have passed all filters will be appended to the FIFO. The FIFO filter path is depicted in Figure 3-129.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 181
FlexRay Module (FLEXRAYV2)
valid frame received (vRF)
store into message buffer (vRF)
yes
individual message buffer found no null frame (vRF!Header!NFIndicator='0') no Frame ID Value-Mask rejection filter passed Frame ID Range rejection filter passed Frame ID Range acceptance filter passed yes
else
else
else
no
frame received in dynamic segment yes
no
message ID (vRF!Header!PPIndicator='1') yes Message ID acceptance filter passed else
append to FIFO (vRF)
no
FIFO full yes set fifo overflow interrupt flag
ignore frame
Figure 3-129. Received Frame FIFO Filter Path
A received frame passes the FIFO filtering if it has passed all three type of filter. 3.4.9.5.1 RX FIFO Frame ID Value-Mask Rejection Filter
The frame ID value-mask rejection filter is a value-mask filter and is defined by the fields in the Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) and the Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR). Each received frame with a frame ID FID that does not match the value-mask filter value passes the filter, i.e. is not rejected. Consequently, a received valid frame with the frame ID FID passes the RX FIFO Frame ID Value-Mask Rejection Filter if Equation 3-10 is fulfilled.
FID & RFFIDRFMR.FIDRFMSK != RFFIDRFVR.FIDRFVAL & RFFIDRFMR.FIDRFMSK Eqn. 3-10
MFR4300 Data Sheet, Rev. 3 182 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
The RX FIFO Frame ID Value-Mask Rejection Filter can be configured to pass all frames by the following settings. * RFFIDRFVR.FIDRFVAL:= 0x000 and RFFIDRFMR.FIDRFMSK:= 0x7FF Using the settings above, only the frame with frame ID 0 will be rejected, which is an invalid frame. All other frames will pass. The RX FIFO Frame ID Value-Mask Rejection Filter can be configured to reject all frames by the following settings. * RFFIDRFMR.FIDRFMSK:= 0x000 Using the settings above, Equation 3-10 can never be fulfilled (0!= 0) and thus all frames are rejected; no frame will pass. This is the reset value for the RX FIFO. 3.4.9.5.2 RX FIFO Frame ID Range Rejection Filter
Each of the four RX FIFO Frame ID Range filters can be configured as a rejection filter. The filters are configured by the Receive FIFO Range Filter Configuration Register (RFRFCFR) and controlled by the Receive FIFO Range Filter Control Register (RFRFCTR). The RX FIFO Frame ID range filters apply to all received valid frames. A received frame with the frame ID FID passes the RX FIFO Frame ID Range rejection filters if either no rejection filter is enabled, or, for all of the enabled RX FIFO Frame ID Range rejection filters, i.e. RFRFCTR.FiMD = 1 and RFRFCTR.FiEN = 1, Equation 3-11 is fulfilled.
FID < RFRFCFRi.SID(0) and RFRFCFRi.SID(1) < FID Eqn. 3-11
Consequently, all frames with a frame ID that fulfills Equation 3-12 for at least one of the enabled rejection filters will be rejected and thus not pass.
RFRFCFRi.SID(0) <= FID <= RFRFCFRi.SID(1) Eqn. 3-12
3.4.9.5.3
RX FIFO Frame ID Range Acceptance filter
Each of the four RX FIFO Frame ID Range filters can be configured as an acceptance filter. The filters are configured by the Receive FIFO Range Filter Configuration Register (RFRFCFR) and controlled by the Receive FIFO Range Filter Control Register (RFRFCTR). The RX FIFO Frame ID range filters apply to all received valid frames. A received frame with the frame ID FID passes the RX FIFO Frame ID Range acceptance filters if either no acceptance filter is enabled, or, for at least one of the enabled RX FIFO Frame ID Range acceptance filters, i.e. RFRFCTR.FiMD = 0 and RFRFCTR.FiEN = 1, Equation 3-13 is fulfilled.
RFRFCFRi.SID(0) <= FID <= RFRFCFRi.SID(1) Eqn. 3-13
3.4.9.5.4
RX FIFO Message ID Acceptance Filter
The RX FIFO Message ID Acceptance Filter is a value-mask filter and is defined by the Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) and the Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR). This filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit PPI set to `1'. All other frames will pass this filter.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 183
FlexRay Module (FLEXRAYV2)
A received valid frame in the dynamic segment with the payload preamble indicator bit PPI set to `1' and with the message ID MID (the first two bytes of the payload) will pass the RX FIFO Message ID Acceptance Filter if Equation 3-14 is fulfilled.
MID & RFMIDAFMR.MIDAFMSK = RFMIDAFVR.MIDAFVAL & RFMIDAFMR.MIDAFMSK Eqn. 3-14
The RX FIFO Message ID Acceptance Filter can be configured to accept all frames by setting * RFMIDAFMR.MIDAFMSK:= 0x000 Using the settings above, Equation 3-14 is always fulfilled and all frames will pass.
3.4.10
Channel Device Modes
This section describes the two FlexRay channel device modes that are supported by the FlexRay module.
3.4.10.1
Dual Channel Device Mode
In the dual channel device mode, both FlexRay ports are connected to physical FlexRay bus lines. The FlexRay port consisting of RXD_BG1, TXD_BG1, and TXEN1# is connected to the physical bus channel A and the FlexRay port consisting of RXD_BG2, TXD_BG2, and TXEN1# is connected to the physical bus channel B. The dual channel system is shown in Figure 3-130.
FlexRay Module
CHI PE RXD_BG1 TXD_BG1 TXEN1#
reg(A) channel 0 cfg(A)
FlexRay Bus Driver Channel A
FlexRay Channel A
cCrcInit[A]
reg(B) channel 1 cfg(B)
RXD_BG2 TXD_BG2 TXEN2#
FlexRay Bus Driver Channel B
FlexRay Channel B
cCrcInit[B]
Figure 3-130. Dual Channel Device Mode
3.4.10.2
Single Channel Device Mode
The single channel device mode supports devices that have only one FlexRay port available. This FlexRay port consists of the signals RXD_BG1, TXD_BG1, and TXEN1# and can be connected to either the physical bus channel A (shown in Figure 3-131) or the physical bus channel B (shown in Figure 3-132).
MFR4300 Data Sheet, Rev. 3 184 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
If the device is configured as a single channel device by setting MCR.SCD to `1', only the internal channel A and the FlexRay Port A is used. Depending on the setting of MCR.CHA and MCR.CHB, the internal channel A behaves either as a FlexRay Channel A or FlexRay Channel B. The bit MCR.CHA must be set, if the FlexRay Port A is connected to a FlexRay Channel A. The bit MCR.CHB must be set if the FlexRay Port A is connected to a FlexRay Channel B. The two FlexRay channels differ only in the initial value for the frame CRC cCrcInit. For a single channel device, the application can access and configure only the registers related to internal channel A.
FlexRay Module
CHI PE RXD_BG1 TXD_BG1 TXEN1#
reg(A) channel A cfg(A)
FlexRay Bus Driver Channel A
FlexRay Channel A
cCrcInit[A]
reg(B) channel B cfg(B)
RXD_BG2 TXD_BG2 TXEN2#
cCrcInit[B]
Figure 3-131. Single Channel Device Mode (Channel A)
FlexRay Module
CHI PE RXD_BG1 TXD_BG1 TXEN1#
reg(A) channel A cfg(A)
FlexRay Bus Driver Channel A
FlexRay Channel B
cCrcInit[A]
Init Value for Frame CRC is cCrcInit[B] RXD_BG2 TXD_BG2 TXEN2#
reg(B) channel B cfg(B)
cCrcInit[B]
Figure 3-132. Single Channel Device Mode (Channel B)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 185
FlexRay Module (FLEXRAYV2)
3.4.11
External Clock Synchronization
The application of the external rate and offset correction is triggered when the application writes to the EOC_AP and ERC_AP fields in the Protocol Operation Control Register (POCR). The PE applies the external correction values in the next even-odd cycle pair as shown in Figure 3-133 and Figure 3-134. If the offset correction applied in the NIT of cycle 2n+1 shall be affect by the external offset correction, the EOC_AP field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle 2n+1. If the value is not applied in cycle 2n+1, then the value will be applied in the cycle 2n+3. Refer to Figure 3-133 for timing details.
EOC_AP write window EOC_AP application
static segment
NIT
static segment
NIT
cycle 2n
cycle 2n+1
Figure 3-133. External Offset Correction Write and Application Timing
If the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the ERC_AP field must be written to after the start of cycle 2n and before the end of the static segment start of cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle pair [2n+2, 2n+3]. If the value is not applied for cycle pair [2n+2, 2n+3], then the value will be applied for cycle pair [2n+4, 2n+5]. Refer to Figure 3-134 for details.
ERC_AP write window ERC_AP application
static segment
NIT
static segment
NIT
static segment
NIT
static segment
NIT
cycle 2n
cycle 2n+1
cycle 2n+2
cycle 2n+3
Figure 3-134. External Rate Correction Write and Application Timing
3.4.12
Sync Frame ID and Sync Frame Deviation Tables
The FlexRay protocol requires the provision of a snapshot of the Synchronization Frame ID tables for the even and odd communication cycle for both channels. The FlexRay module provides the means to write a copy of these internal tables into the FRM and ensures application access to consistent tables by means of table locking. Once the application has locked the table successfully, the FlexRay module will not overwrite these tables and the application can read a consistent snapshot. NOTE Only synchronization frames that have passed the synchronization frame filters are considered for clock synchronization and appear in the sync frame tables.
MFR4300 Data Sheet, Rev. 3 186 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.4.12.1
Sync Frame ID Table Content
The Sync Frame ID Table is a snapshot of the protocol related variables vsSyncIdListA and vsSyncIdListB for each even and odd communication cycle. This table provides a list of the frame IDs of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization.
3.4.12.2
Sync Frame Deviation Table Content
The Sync Frame Deviation Table is a snapshot of the protocol related variable zsDev(id)(oe)(ch)!Value. Each Sync Frame Deviation Table entry provides the deviation value for the sync frame, with the frame ID presented in the corresponding entry in the Sync Frame ID Table.
SFTOR EVEN SFCNTR
SFEVA SFEVB Offset + $00 Offset + $02 Offset + $04 Offset + $06 Offset + $08 Offset + $0A Offset + $0C Offset + $0E Offset + $10 Offset + $12 Offset + $14 Offset + $16 Offset + $18 Offset + $1A Offset + $1C Offset + $1E Offset + $20 Offset + $22 Offset + $24 Offset + $26 Offset + $28 Offset + $2A Offset + $2C Offset + $2E Offset + $30 Offset + $32 Offset + $34 Offset + $36 Offset + $38 Offset + $3A
SFTOR + 60
SFTOR +120 ODD
SFTOR + 180 EVEN ODD
Sync Deviation ChA 1 Sync Deviation ChA 2 Sync Deviation ChA 3 Sync Deviation ChA 4 Sync Deviation ChA 5 Sync Deviation ChA 6 Sync Deviation ChA 7 Sync Deviation ChA 8 Sync Deviation ChA 9 Sync Deviation ChA 10 Sync Deviation ChA 11 Sync Deviation ChA 12 Sync Deviation ChA 13 Sync Deviation ChA 14 Sync Deviation ChA 15 Sync Deviation ChB 1 Sync Deviation ChB 2 Sync Deviation ChB 3 Sync Deviation ChB 4 Sync Deviation ChB 5 Sync Deviation ChB 6 Sync Deviation ChB 7 Sync Deviation ChB 8 Sync Deviation ChB 9 Sync Deviation ChB 10 Sync Deviation ChB 11 Sync Deviation ChB 12 Sync Deviation ChB 13 Sync Deviation ChB 14 Sync Deviation ChB 15
SFCNTR
SFODA SFODB
Sync Frame ID ChA 1 Sync Frame ID ChA 2 Sync Frame ID ChA 3 Sync Frame ID ChA 4 Sync Frame ID ChA 5 Sync Frame ID ChA 6 Sync Frame ID ChA 7 Sync Frame ID ChA 8 Sync Frame ID ChA 9 Sync Frame ID ChA 10 Sync Frame ID ChA 11 Sync Frame ID ChA 12 Sync Frame ID ChA 13 Sync Frame ID ChA 14 Sync Frame ID ChA 15 Sync Frame ID ChB 1 Sync Frame ID ChB 2 Sync Frame ID ChB 3 Sync Frame ID ChB 4 Sync Frame ID ChB 5 Sync Frame ID ChB 6 Sync Frame ID ChB 7 Sync Frame ID ChB 8 Sync Frame ID ChB 9 Sync Frame ID ChB 10 Sync Frame ID ChB 11 Sync Frame ID ChB 12 Sync Frame ID ChB 13 Sync Frame ID ChB 14 Sync Frame ID ChB 15
Sync Frame ID ChA 1 Sync Frame ID ChA 2 Sync Frame ID ChA 3 Sync Frame ID ChA 4 Sync Frame ID ChA 5 Sync Frame ID ChA 6 Sync Frame ID ChA 7 Sync Frame ID ChA 8 Sync Frame ID ChA 9 Sync Frame ID ChA 10 Sync Frame ID ChA 11 Sync Frame ID ChA 12 Sync Frame ID ChA 13 Sync Frame ID ChA 14 Sync Frame ID ChA 15 Sync Frame ID ChB 1 Sync Frame ID ChB 2 Sync Frame ID ChB 3 Sync Frame ID ChB 4 Sync Frame ID ChB 5 Sync Frame ID ChB 6 Sync Frame ID ChB 7 Sync Frame ID ChB 8 Sync Frame ID ChB 9 Sync Frame ID ChB 10 Sync Frame ID ChB 11 Sync Frame ID ChB 12 Sync Frame ID ChB 13 Sync Frame ID ChB 14 Sync Frame ID ChB 15
Sync Deviation ChA 1 Sync Deviation ChA 2 Sync Deviation ChA 3 Sync Deviation ChA 4 Sync Deviation ChA 5 Sync Deviation ChA 6 Sync Deviation ChA 7 Sync Deviation ChA 8 Sync Deviation ChA 9 Sync Deviation ChA 10 Sync Deviation ChA 11 Sync Deviation ChA 12 Sync Deviation ChA 13 Sync Deviation ChA 14 Sync Deviation ChA 15 Sync Deviation ChB 1 Sync Deviation ChB 2 Sync Deviation ChB 3 Sync Deviation ChB 4 Sync Deviation ChB 5 Sync Deviation ChB 6 Sync Deviation ChB 7 Sync Deviation ChB 8 Sync Deviation ChB 9 Sync Deviation ChB 10 Sync Deviation ChB 11 Sync Deviation ChB 12 Sync Deviation ChB 13 Sync Deviation ChB 14 Sync Deviation ChB 15
Figure 3-135. Sync Table Memory Layout
3.4.12.3
Sync Frame ID and Sync Frame Deviation Table Setup
The FlexRay module writes a copy of the internal synchronization frame ID and deviation tables into the FRM if requested by the application. The application must provide the appropriate amount of FRM for the tables. The memory layout of the tables is given in Figure 3-135. Each table occupies 120 16-bit entries. While the protocol is in POC:config state, the application must program the offsets for the tables into the Sync Frame Table Offset Register (SFTOR).
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 187
FlexRay Module (FLEXRAYV2)
3.4.12.4
Sync Frame ID and Sync Frame Deviation Table Generation
The application controls the generation process of the Sync Frame ID and Sync Frame Deviation Tables into the FRM using the Sync Frame Table Configuration, Control, Status Register (SFTCCSR). A summary of the copy modes is given in Table 3-108.
Table 3-108. Sync Frame Table Generation Modes
SFTCCSR Description OPT 0 0 0 0 1 1 0 1 SDVEN 0 0 1 1 0 0 1 1 SIDEN 0 1 0 1 0 1 0 1 No Sync Frame Table copy Sync Frame ID Tables will be copied continuously Reserved Sync Frame ID Tables and Sync Frame Deviation Tables will be copied continuously No Sync Frame Table copy Sync Frame ID Tables for next even-odd-cycle pair will be copied Reserved Sync Frame ID Tables and Sync Frame Deviation Tables for next even-odd-cycle pair will be copied
The Sync Frame Table generation process is described in the following for the even cycle. The same sequence applies to the odd cycle. If the application has enabled the sync frame table generation by setting SFTCCSR.SIDEN to `1', the FlexRay module starts the update of the even cycle related tables after the start of the NIT of the next even cycle. The FlexRay module checks if the application has locked the tables by reading the SFTCCSR.ELKS lock status bit. If this bit is set, the FlexRay module will not update the table in this cycle. If this bit is cleared, the FlexRay module locks this table and starts the table update. To indicate that these tables are currently updated and may contain inconsistent data, the FlexRay module clears the even table valid status bit SFTCCSR.EVAL. Once all table entries related to the even cycle have been transferred into the FRM, the FlexRay module sets the even table valid bit SFTCCSR.EVAL and the Even Cycle Table Written Interrupt Flag EVT_IF in the Protocol Interrupt Flag Register 1 (PIFR1). If the interrupt enable flag EVT_IE is set, an interrupt request is generated. To read the generated tables, the application must lock the tables to prevent the FlexRay module from updating these tables. The locking is initiated by writing a `1' to the even table lock trigger SFTCCSR.ELKT. When the even table is not currently updated by the FlexRay module, the lock is granted and the even table lock status bit SFTCCSR.ELKS is set. This indicates that the application has successfully locked the even sync tables and the corresponding status information fields SFRA, SFRB in the Sync Frame Counter Register (SFCNTR). The value in the SFTCCSR.CYCNUM field provides the number of the cycle that this table is related to. The number of available table entries per channel is provided in the SFCNTR.SFEVA and SFCNTR.SFEVB fields. The application can now start to read the sync table data from the locations given in Figure 3-135. After reading all the data from the locked tables, the application must unlock the table by writing to the even table lock trigger SFTCCSR.ELKT again. The even table lock status bit SFTCCSR.ELKS is reset immediately.
MFR4300 Data Sheet, Rev. 3 188 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
If the sync frame table generation is disabled, the table valid bits SFTCCSR.EVAL and SFTCCSR.EVAL are reset when the counter values in the Sync Frame Counter Register (SFCNTR) are updated. This is done because the tables stored in the FRM are no longer related to the values in the Sync Frame Counter Register (SFCNTR).
even table write SFTCCSR.[OPT,SIDEN,SDVEN] write window odd table write
static segment
NIT
static segment
NIT
static segment
NIT
cycle 2n-1
cycle 2n
cycle 2n+1
Figure 3-136. Sync Frame Table Trigger and Generation Timing
3.4.12.5
Sync Frame Table Access
The sync frame tables will be transferred into the FRM during the table write windows shown in Figure 3-136. During the table write, the application can not lock the table that is currently written. If the application locks the table outside of the table write window, the lock is granted immediately. 3.4.12.5.1 Sync Frame Table Locking and Unlocking
The application locks the even/odd sync frame table by writing `1' to the lock trigger bit ELKT/OLKT in the Sync Frame Table Configuration, Control, Status Register (SFTCCSR). If the affected table is not currently written to the FRM, the lock is granted immediately, and the lock status bit ELKS/OLKS is set. If the affected table is currently written to the FRM, the lock is not granted. In this case, the application must issue the lock request again until the lock is granted. The application unlocks the even/odd sync frame table by writing `1' to the lock trigger bit ELKT/OLKT. The lock status bit ELKS/OLKS is cleared immediately.
3.4.13
MTS Generation
The FlexRay module provides a flexible means to request the transmission of the Media Access Test Symbol MTS in the symbol window on channel A or channel B. The application can configure the set of communication cycles in which the MTS will be transmitted over the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the MTS A Configuration Register (MTSACFR) and MTS B Configuration Register (MTSBCFR). The application enables or disables the generation of the MTS on either channel by setting or clearing the MTE control bit in the MTS A Configuration Register (MTSACFR) or MTS B Configuration Register (MTSBCFR). If an MTS is to be transmitted in a certain communication cycle, the application must set the MTE control bit during the static segment of the preceding communication cycle. The MTS is transmitted over channel A in the communication cycle with number CCN, if Equation 3-16, Equation 3-17, and Equation 3-17 are fulfilled.
PSR0.PROTSTATE = NORMAL_ACTIVE MTSACFR.MTE = 1
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 189
Eqn. 3-15 Eqn. 3-16
FlexRay Module (FLEXRAYV2)
CCN[5:0] & MTSACFR.CCFMSK[5:0]== MTSACFR.CCFVAL[5:0] & MTSACFR.CCFMSK[5:0]
Eqn. 3-17
The MTS is transmitted over channel B in the communication cycle with number CCN, if Equation 3-15, Equation 3-18, and Equation 3-19 are fulfilled.
MTSBCFR.MTE = 1 CCN[5:0] & MTSBCFR.CCFMSK[5:0] = MTSBCFR.CCFVAL[5:0] & MTSBCFR.CCFMSK[5:0] Eqn. 3-18 Eqn. 3-19
3.4.14
Sync Frame and Startup Frame Transmission
The transmission of sync frames and startup frames is controlled by the following register fields: * PCR18.key_slot_id: provides the number of the slot for sync or startup frame transmission * PCR11.key_slot_used_for_sync: indicates sync frame transmission * PCR11.key_slot_used_for_startup: indicates startup frame transmission * PCR12.key_slot_header_crc: provides header crc for sync frame or startup frame * Message Buffer with message buffer number n=PCR18.key_slot_id The generation of the sync or startup frames depends on the current protocol state. In the POC:startup state, the generation is independent of the message buffer setup; in the POC:normal active state, the generation is affected by the current message buffer setup.
3.4.14.1
Sync Frame and Startup Frame Transmission in POC:startup
In the POC:startup state, the sync and startup frame transmission is independent of the message buffer setup. If at least one of the indication bits PCR11.key_slot_used_for_sync or PCR11.key_slot_used_for_startup is set, a Null Frame will be transmitted in the slot with slot number PCR18.key_slot_id. The header CRC for this Null Frame is taken from PCR12.key_slot_header_crc. The settings of the sync and startup frame indicators are taken from PCR11.key_slot_used_for_sync and PCR11.key_slot_used_for_startup.
3.4.14.2
Sync Frame and Startup Frame Transmission in POC:normal active
In the POC:normal active state, the sync and startup frame transmission depends on the message buffer setup. If at least one of the indication bits PCR11.key_slot_used_for_sync or PCR11.key_slot_used_for_startup is set, or if a transmit message buffer with MBFIDRn.FID == PCR18.key_slot_id is configured and enabled, a Null Frame or Data Frame will be transmitted in the slot with slot number PCR18.key_slot_id. The header CRC for this frame is taken from PCR12.key_slot_header_crc, the settings of the sync and startup frame indicators are taken from PCR11.key_slot_used_for_sync and PCR11.key_slot_used_for_startup. A data frame will be transmitted if the message buffer is unlocked and committed and the cycle counter filter matches the current cycle.
3.4.15
Sync Frame Filtering
Each received synchronization frame must pass the Sync Frame Acceptance Filter and the Sync Frame Rejection Filter before it is considered for clock synchronization. If the synchronization frame filtering is
MFR4300 Data Sheet, Rev. 3 190 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
globally disabled, i.e. the SFFE control bit in the Module Configuration Register (MCR) is cleared, all received synchronization frames are considered for clock synchronization. If a received synchronization frame did not pass at least one of the two filters, this frame is processed as a normal frame and is not considered for clock synchronization.
3.4.15.1
Sync Frame Acceptance Filtering
The synchronization frame acceptance filter is implemented as a value-mask filter. The value is configured in the Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) and the mask is configured in the Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR). A received synchronization frame with the frame ID FID passes the sync frame acceptance filter, if Equation 3-20 or Equation 3-21evaluates to true.
MCR.SFFE == 0 FID [ 9:0 ] & SFIDAFMR.FMSK[9:0] == SFIDAFVR.FVAL[9:0] & SFIDAFMR.FMSK[9:0] Eqn. 3-20 Eqn. 3-21
NOTE Sync frames are transmitted in the static segment only. Thus FID <= 1023.
3.4.15.2
Sync Frame Rejection Filtering
The synchronization frame rejection filter is a comparator. The compare value is defined by the Sync Frame ID Rejection Filter Register (SFIDRFR). A received synchronization frame with the frame ID FID passes the sync frame rejection filter if Equation 3-22 or Equation 3-23 evaluates to true.
MCR.SFFE == 0 FID [ 9:0 ] != SFIDRFR.SYNFRID[9:0] Eqn. 3-22 Eqn. 3-23
NOTE Sync frames are transmitted in the static segment only. Thus FID <= 1023.
3.4.16
Strobe Signal Support
The FlexRay module provides a number of strobe signals for observing internal protocol timing related signals in the protocol engine. The signals are listed and described in Table 3-11.
3.4.16.1
Strobe Signal Assignment
Each of the strobe signals listed in Table 3-11 can be assigned to one of the four strobe ports using the Strobe Signal Control Register (STBSCR). To assign multiple strobe signals, the application must write multiple times to the Strobe Signal Control Register (STBSCR) with appropriate settings. To read out the current settings for a strobe signal with number N, the application must execute the following sequence. 1. Write to STBSCR with WMD = 1 and SEL = N. (updates SEL field only)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 191
FlexRay Module (FLEXRAYV2)
2. Read STBCSR. The SEL field provides N and the ENB and STBPSEL fields provides the settings for signal N.
3.4.16.2
Strobe Signal Timing
This section provides detailed timing information of the strobe signals with respect to the protocol engine clock. The strobe signals display internal PE signals. Due to the internal architecture of the PE, some signals are generated several PE clock cycles before the actual action is performed on the FlexRay Bus. These signals are listed in Table 3-11 with a negative clock offset. An example waveform is given in Figure 3-137.
PE Clock Strobe Signal FlexRay Bus Event -2
Figure 3-137. Strobe Signal Timing (type = pulse, clk_offset = -2)
Other signals refer to events that occurred on the FlexRay Bus some cycles before the strobe signal is changed. These signals are listed in Table 3-11 with a positive clock offset. An example waveform is given in Figure 3-138.
PE Clock Strobe Signal FlexRay Bus Event +4
Figure 3-138. Strobe Signal Timing (type = pulse, clk_offset = +4)
3.4.17
Timer Support
The FlexRay module provides two timers, which run on the FlexRay time base. Each timer generates a maskable interrupt when it reaches a configured point in time. Timer T1 is an absolute timer. Timer T2 can be configured to be an absolute or a relative timer. Both timers can be configured to be repetitive. In the non-repetitive mode, timer stops if it expires. In repetitive mode, timer is restarted when it expires. Both timers are active only when the protocol is in POC:normal active or POC:normal passive state. If the protocol is not in one of these modes, the timers are stopped. The application must restart the timers when the protocol has reached the POC:normal active or POC:normal passive state.
MFR4300 Data Sheet, Rev. 3 192 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.4.17.1
Absolute Timer T1
The absolute timer T1 has the protocol cycle count and the macrotick count as the time base. The timer 1 interrupt flag TI1_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set at the macrotick start event, if Equation 3-24 and Equation 3-25 are fulfilled
CYCCTR.CYCCNT & T1CYSR.T1_CYC_MSK == T1CYSR.T1_CYC_VAL & T1CYSR.T1_CYC_MSK Eqn. 3-24 MTCTR.MTCT == TI1MTOR.T1_MTOFFSET Eqn. 3-25
If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 (PIER0) is asserted, an interrupt request is generated. The status bit T1ST is set when the timer is triggered, and is cleared when the timer expires and is non-repetitive. If the timer expires but is repetitive, the T1ST bit is not cleared and the timer is restarted immediately. The T1ST is cleared when the timer is stopped.
3.4.17.2
Absolute / Relative Timer T2
The timer T2 can be configured to be an absolute or relative timer by setting the T2_CFG control bit in the Timer Configuration and Control Register (TICCR). The status bit T2ST is set when the timer is triggered, and is cleared when the timer expires and is non-repetitive. If the timer expires but is repetitive, the T2ST bit is not cleared and the timer is restarted immediately. The T2ST is cleared when the timer is stopped. 3.4.17.2.1 Absolute Timer T2
If timer T2 is configured as an absolute timer, it has the same functionality timer T1 but the configuration from Timer 2 Configuration Register 0 (TI2CR0) and Timer 2 Configuration Register 1 (TI2CR1) is used. On expiration of timer T2, the interrupt flag TI2_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set. If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 (PIER0) is asserted, an interrupt request is generated. 3.4.17.2.2 Relative Timer T2
If the timer T2 is configured as a relative timer, the interrupt flag TI2_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set, when the programmed amount of macroticks MT[31:0], defined by Timer 2 Configuration Register 0 (TI2CR0) and Timer 2 Configuration Register 1 (TI2CR1), has expired since the trigger or restart of timer 2. The relative timer is implemented as a down counter and expires when it has reached 0. At the macrotick start event, the value of MT[31:0] is checked and then decremented. Thus, if the timer is started with MT[31:0] == 0, it expires at the next macrotick start.
3.4.18
Slot Status Monitoring
The FlexRay module provides several means for slot status monitoring. All slot status monitors use the same slot status vector provided by the PE. The PE provides a slot status vector for each static slot, for each dynamic slot, for the symbol window, and for the NIT, on a per channel base. The content of the slot status vector is described in Table 3-109. The PE provides the slot status vector within the first macrotick after the end of the related slot/window/NIT, as shown in Figure 3-139.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 193
FlexRay Module (FLEXRAYV2)
status(slot 1)
status(sym.win)
status(slot k)
status(slot n)
status(NIT)
symbol window start
cycle start
cycle start NIT
slot start MT
NIT start
slot start
MT
MT
slot 1 static segment dynamic segment
MT
symbol window
communication cycle
Figure 3-139. Slot Status Vector Update
NOTE The slot status for the NIT of cycle n is provided after the start of cycle n+1.
Table 3-109. Slot Status Content
Status Content static / dynamic Slot slot related status vSS!ValidFrame - valid frame received vSS!SyntaxError - syntax error occurred while receiving vSS!ContentError - content error occurred while receiving vSS!BViolation - boundary violation while receiving for slots in which the module transmits: vSS!TxConflict - reception ongoing while transmission starts for slots in which the module does not transmit: vSS!TxConflict - reception ongoing while transmission starts first valid - channel that has received the first valid frame received frame related status extracted from a) header of valid frame, if vSS!ValidFrame = 1 b) last received header, if vSS!ValidFrame = 0 c) set to `0', if nothing was received vRF!Header!NFIndicator - Null Frame Indicator (0 for null frame) vRF!Header!SuFIndicator - Startup Frame Indicator vRF!Header!SyFIndicator - Sync Frame Indicator
MFR4300 Data Sheet, Rev. 3 194 Freescale Semiconductor
MT
MT
status(NIT)
FlexRay Module (FLEXRAYV2)
Table 3-109. Slot Status Content
Status Content Symbol Window window related status vSS!ValidFrame - always 0 vSS!ContentError - content error occurred while receiving vSS!SyntaxError - syntax error occurred while receiving vSS!BViolation - boundary violation while receiving vSS!TxConflict - reception ongoing while transmission starts received symbol related status vSS!ValidMTS - valid Media Test Access Symbol received received frame related status see static/dynamic slot NIT related status vSS!ValidFrame - always 0 vSS!ContentError - content error occurred while receiving vSS!SyntaxError - syntax error occurred while receiving vSS!BViolation - boundary violation while receiving vSS!TxConflict - always 0 received frame related status see static/dynamic slot
NIT
3.4.18.1
Channel Status Error Counter Registers
The two channel status error counter registers, Channel A Status Error Counter Register (CASERCR) and Channel B Status Error Counter Register (CBSERCR), incremented by one, if at least one of four slot status error bits, vSS!SyntaxError, vSS!ContentError, vSS!BViolation, or vSS!TxConflict is set to `1'. The status vectors for all slots in the static and dynamic segment, in the symbol window, and in the NIT are taken into account. The counters wrap round after they have reached the maximum value.
3.4.18.2
Protocol Status Registers
The Protocol Status Register 2 (PSR2) provides slot status information about the Network Idle Time NIT and the Symbol Window. The Protocol Status Register 3 (PSR3) provides aggregated slot status information.
3.4.18.3
Slot Status Registers
The eight slot status registers, Slot Status Registers (SSR0-SSR7), can be used to observe the status of static slots, dynamic slots, the symbol window, or the NIT without individual message buffers. These registers provide all slot status related and received frame / symbol related status information, as given in Table 3-109, except of the first valid indicator for non-transmission slots.
3.4.18.4
Slot Status Counter Registers
The FlexRay module provides four slot status error counter registers, Slot Status Counter Registers (SSCR0-SSCR3). Each of these slot status counter registers is updated with the value of an internal slot status counter at the start of a communication cycle. The internal slot status counter is incremented if its increment condition, defined by the Slot Status Counter Condition Register (SSCCR), matches the status
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 195
FlexRay Module (FLEXRAYV2)
vector provided by the PE. All static slots, the symbol window, and the NIT status are taken into account. Dynamic slots are excluded. The internal slot status counting and update timing is shown in Figure 3-140.
incr. SSCRn_INT on error SSCRn_INT not updated incr. SSCRn_INT on error
SSCRn:= SSCRn_INT status(slot 1) status(slot n) status(slot k) status(NIT)
status(sym.win)
SSCRn:= SSCRn_INT status(NIT) cycle start NIT
symbol window start
cycle start
slot start MT
slot start
NIT start
MT
MT
slot 1 static segment dynamic segment
MT
symbol window
communication cycle
Figure 3-140. Slot Status Counting and SSCRn Update
The PE provides the status of the NIT in the first slot of the next cycle. Due to these facts, the SSCRn register reflects, in cycle n, the status of the NIT of cycle n-2, and the status of all static slots and the symbol window of cycle n-1. The increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least one of the conditions is fulfilled: 1. frame related condition: * (SSCCRn.VFR | SSCCRn.SYF | SSCCRn.NUF | SSCCRn.SUF) // count on frame condition = `1'; and * ((~SSCCRn.VFR | vSS!ValidFrame) & // valid frame restriction (~SSCCRn.SYF | vRF!Header!SyFIndicator) & // sync frame indicator restriction (~SSCCRn.NUF | ~vRF!Header!NFIndicator) & // null frame indicator restriction (~SSCCRn.SUF | vRF!Header!SuFIndicator)) // startup frame indicator restriction = `1'; NOTE The indicator bits SYF, NUF, and SUF are valid only when a valid frame was received. Thus it is required to set the VFR always, whenever count on frame condition is used. 2. slot related condition: * ((SSCCRn.STATUSMASK[3] & vSS!ContentError) | // increment on content error (SSCCRn.STATUSMASK[2] & vSS!SyntaxError) | // increment on syntax error (SSCCRn.STATUSMASK[1] & vSS!BViolation) | // increment on boundary violation
MFR4300 Data Sheet, Rev. 3 196 Freescale Semiconductor
MT
MT
FlexRay Module (FLEXRAYV2)
(SSCCRn.STATUSMASK[0] & vSS!TxConflict)) // increment on transmission conflict = `1'; If the slot status counter is in single cycle mode, i.e. SSCCRn.MCY = `0', the internal slot status counter SSCRn_INT is reset at each cycle start. If the slot status counter is in the multicycle mode, i.e. SSCCRn.MCY = `1', the counter is not reset and incremented, until the maximum value is reached.
3.4.18.5
Message Buffer Slot Status Field
Each individual message buffer and each FIFO message buffer provides a slot status field, which provides the information shown in Table 3-109 for the static/dynamic slot. The update conditions for the slot status field depend on the message buffer type. Refer to the Message Buffer Update Sections in Section 3.4.6, "Individual Message Buffer Functional Description".
3.4.19
Interrupt Support
The FlexRay module provides 172 individual interrupt sources and five combined interrupt sources.
3.4.19.1
3.4.19.1.1
Individual Interrupt Sources
Message Buffer Interrupts
The FlexRay module provides 128 message buffer interrupt sources. Each individual message buffer provides an interrupt flag MBCCSn.MBIF and an interrupt enable bit MBCCSn.MBIE. The FlexRay module sets the interrupt flag when the slot status of the message buffer was updated. If the interrupt enable bit is asserted, an interrupt request is generated. 3.4.19.1.2 Receive FIFO Interrupts
The FlexRay module provides 2 Receive FIFO interrupt sources. Each of the 2 Receive FIFO provides a Receive FIFO Not Empty Interrupt Flag. The FlexRay module sets the Receive FIFO Not Empty Interrupt Flags (GIFER.FNEBIF, GIFER.FNEAIF) in the Global Interrupt Flag and Enable Register (GIFER) if the corresponding Receive FIFO is not empty. 3.4.19.1.3 Wakeup Interrupt
The FlexRay module provides one interrupt source related to the wakeup. The FlexRay module sets the Wakeup Interrupt Flag GIFER.WUPIF when it has received a wakeup symbol on the FlexRay bus. The FlexRay module generates an interrupt request if the interrupt enable bit GIFER.WUPIE is asserted. 3.4.19.1.4 Protocol Interrupts
The FlexRay module provides 25 interrupt sources for protocol related events. For details, see Protocol Interrupt Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1). Each interrupt source has its own interrupt enable bit.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 197
FlexRay Module (FLEXRAYV2)
3.4.19.1.5
CHI Error Interrupts
The FlexRay module provides 16 interrupt sources for CHI related error events. For details, see CHI Error Flag Register (CHIERFR). There is one common interrupt enable bit GIFER.CHIIE for all CHI error interrupt sources.
3.4.19.2
Combined Interrupt Sources
Each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined generates an interrupt request. 3.4.19.2.1 Receive Message Buffer Interrupt
The combined receive message buffer interrupt request RBIRQ is generated when at least one of the individual receive message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit GIFER.RBIE is set. 3.4.19.2.2 Transmit Message Buffer Interrupt
The combined transmit message buffer interrupt request TBIRQ is generated when at least one of the individual transmit message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit GIFER.TBIE is asserted. 3.4.19.2.3 Protocol Interrupt
The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set. 3.4.19.2.4 CHI Error Interrupt
The combined CHI error interrupt interrupt request CHIIRQ is generated when at least one of the individual chi error interrupt sources generates an interrupt request and the interrupt enable bit GIFER.CHIE is set. 3.4.19.2.5 Module Interrupt
The combined module interrupt request MIRQ is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit GIFER.MIE is set.
MFR4300 Data Sheet, Rev. 3 198 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Interrupt Sources
MBCCSRn.MBIF MBCCSRn.MBIE CHIER[15:0] GIFER.CHIE PIFR0[15:0] PIER0[15:0] PIFR1[15:0] PIER1[15:0] MBCCSRn.MTD & & & & & n
n = # Message Buffers
Interrupt Signals
MBXIRQ[n-1:0]
16
CHIXIRQ[15:0]
16
PRTXIRQ[31:16]
16
PRTXIRQ[15:0]
n Receive n & Transmit
GIFER.RBIF OR GIFER.RBIE GIFER.TBIF OR GIFER.TBIE & &
RBIRQ
TBIRQ
OR
GIFER.CHIF
CHIIRQ
GIFER.PRIF OR GIFER.FNEAIF GIFER.FNEAIE GIFER.FNEBIF GIFER.FNEBIE GIFER.WUPIF GIFER.WUPIE & & & GIFER.PRIE &
PRTIRQ
FNEAIRQ
FNEBIRQ
WUPIRQ GIFER.MIF OR & GIFER.MIE MIRQ
Figure 3-141. Scheme of cascaded interrupt request
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 199
FlexRay Module (FLEXRAYV2)
MIRQ CRSR.LVIF CRSR.CMIF CRSR.PRIF CRSR.ERIF Figure 3-142. INT_CC# generation scheme OR INT_CC#
Interrupt Sources
MBCCSRn.MTD n
n = # Message Buffers n &
Transmit
Combined Interrupt Flags
CIFR.TBIF
MBCCSRn.MBIF
OR
n &
Receive
OR
CIFR.RBIF
CHIER[15:0]
OR
CIFR.CHIF
PIFR0[15:0] PIFR1[15:0] OR CIFR.PRIF
OR GIFER.FNEAIF GIFER.FNEBIF GIFER.WUPIF
CIFR.MIF
CIFR.FNEAIF CIFR.FNEBIF CIFR.WUPIF Figure 3-143. Scheme of combined interrupt flags
MFR4300 Data Sheet, Rev. 3 200 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
3.4.20
Clock Domain Crossing
The Clock Domain Crossing module CDC implements the signal crossing from the CHI clock domain to the PE clock domain and vice versa. The signal crossing logic is implemented as a three-stage pipe-line. Two pipe-line stages are used for clock synchronization; the third stage is used for pulse generation.
3.4.20.1
Clock Domain Crossing Signal Latency
Due to the clock domain crossing implementation, each signal from the PE to the CHI is delayed by at least two CHI clock cycles and by at most three CHI clock cycles. In terms of time, the signal latency time tlat for a given CHI frequency fchi is
2 3 ------- t ------f chi lat f chi Eqn. 3-26
3.5
Initialization Information
This section provides information for initializing and using the FlexRay module.
3.5.1
FlexRay Initialization Sequence
The full FlexRay module is reset with the hard reset. Additionally, the protocol engine is reset in the Stop Mode and as a result of the RESET protocol command issued using the Protocol Operation Control Register (POCR). The hard reset resets all internal registers and all registers in the FlexRay module memory map. The protocol engine reset resets only the registers in the protocol engine. All registers in memory are not reset. The following is an initialization sequence applicable to the FlexRay module after a hard reset 1. Configure FlexRay module -- set the control bits in the Module Configuration Register (MCR) 2. Enable the FlexRay module -- set the MEN bit in the Module Configuration Register (MCR) -- the FlexRay module enters the Normal Mode 3. Configure the Protocol Engine -- write the CONFIG command into the POCCMD field of the Protocol Operation Control Register (POCR) -- write to the PCR[0:31] registers to set all protocol parameters. 4. Configure the Message Buffers and FIFOs -- set the number of message buffers used and the message buffer segmentation in the Message Buffer Segment Size and Utilization Register (MBSSUTR) -- define the message buffer data size in the Message Buffer Data Size Register (MBDSR) -- configure each message buffer by setting the configuration values in the Message Buffer Configuration, Control, Status Registers (MBCCSRn), Message Buffer Cycle Counter Filter Registers (MBCCFRn), Message Buffer Frame ID Registers (MBFIDRn), Message Buffer Index Registers (MBIDXRn)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 201
FlexRay Module (FLEXRAYV2)
-- configure the receive FIFOs 5. Start the FlexRay module as a FlexRay node -- write the READY protocol command into the POCCMD field of the Protocol Operation Control Register (POCR) -- now the FlexRay module enters the FlexRay protocol After this sequence, the FlexRay module is configured as a FlexRay node and is ready to be integrated into the FlexRay cluster.
3.5.2
Number of Usable Message Buffers
This section describes how to determine the number of message buffers that can be utilized at a given CHI clock frequency fchi. The FlexRay module uses a sequential search to determine the individual message buffers suitable for transmission or reception in the next slot. This search must be finished within one FlexRay slot. The shortest FlexRay slot is an empty dynamic slot. An empty dynamic slot is a minislot and consists of at least two macroticks. The minimum length of a corrected macrotick is 39 T. The length of 1 T is 25 ns. This results in a minimum slot length of
ns T t slotmin = 1.95s = 25 ------ 39 -------- 2MT T MT Eqn. 3-27
The search engine is located in the CHI and runs on the CHI clock. The search engine searches one individual message buffer per clock cycle. For internal status update and double buffer commit operations, and as a result of the clock domain crossing jitter, an additional amount of 10 clock cycles is required to ensure correct operation. For a given number of message buffers and for a given CHI clock frequency fchi, this results in a search duration of
1 t search = ------- ( messagebuffers + 10 ) f chi Eqn. 3-28
As mentioned above, each message buffer search must be finished within one slot. Thus the following equation must be fulfilled
t search t slotmin Eqn. 3-29
This results in the formula to determine the minimum required CHI frequency for a given number of message buffers that can be utilized.
messagebuffers + 10 f chi -------------------------------------------------------1.95s Table 3-110. Minimum CHI Frequency Examples
# Message Buffers minimum fchi 32 21.54 MHz
Eqn. 3-30
The minimum CHI frequency for a selected set of message buffer numbers is given in Table 3-110.
MFR4300 Data Sheet, Rev. 3 202 Freescale Semiconductor
FlexRay Module (FLEXRAYV2)
Table 3-110. Minimum CHI Frequency Examples
# Message Buffers minimum fchi 64 128 37.95 MHz 70.77 MHz
3.6
3.6.1
Application Information
Shut Down Sequence
This section describes a safe shut down sequence to stop the FlexRay module gracefully. The main targets of this sequence are * do not send invalid data on the FlexRay bus * do not corrupt FlexRay bus and do not disturb ongoing communication * finish all ongoing reception Firstly, the application must disable all message buffers by triggering the EDT trigger bit in the Message Buffer Configuration, Control, Status Registers (MBCCSRn), until the EDS flag is cleared by the FlexRay module. This ensures that no transmission is started by the FlexRay module. If all message buffers are disabled, the application issues the HALT command to the PE using the Protocol Operation Control Register (POCR). The PE then waits for the end of the communication cycle and goes into the POC:halt state. The application can observe this state change in the PROTSTATE field of the Protocol Status Register 0 (PSR0).
3.6.2
Protocol Control Command Execution
This section considers the issues of the protocol control command execution. The application issues any of the protocol control commands listed in the POCCMD field of Table 3-15 by writing the command to the POCCMD field of the Protocol Operation Control Register (POCR). As a result the FlexRay module sets the BSY bit while the command is transferred to the PE. When the PE has accepted the command, the BSY flag is cleared. All commands are accepted by the PE. The PE maintains a protocol command vector. For each command that was accepted by the PE, the PE sets the corresponding command bit in the protocol command vector. If a command is issued while the corresponding command bit is set, the command is not queued and is lost. If the command execution block of the PE is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in Table 3-111. If the current protocol state does not allow the execution of this protocol command (see POC state changes in FlexRay Communications System Protocol Specification, Version 2.1) the FlexRay module asserts the illegal protocol command interrupt flag IPC_IF in the Protocol Interrupt Flag Register 1 (PIFR1). The protocol command is not executed in this case. Some protocol commands may be interrupted by other commands or the detection of a fatal protocol error as indicated by Table 3-111. If the application issues the RESET, FREEZE, or READY command, or if the
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 203
FlexRay Module (FLEXRAYV2)
the PE detects a fatal protocol error, some commands already stored in the command vector will be removed from this vector.
Table 3-111. Protocol Control Command Priorities
Protocol Command RESET FREEZE READY CONFIG_COMPLETE ALL_SLOTS ALLOW_COLDSTART RUN WAKEUP DEFAULT_CONFIG CONFIG HALT Priority (highest) 1 2 3 3 4 5 RESET, FREEZE, READY, 7 CONFIG_COMPLET, fatal protocol error 6 8 9 (lowest) 10 none RESET RESET RESET RESET, FREEZE, READY, CONFIG_COMPLETE, fatal protocol error RESET RESET, FREEZE, fatal protocol error RESET, FREEZE, fatal protocol error RESET, FREEZE, fatal protocol error RESET RESET, FREEZE, READY, CONFIG_COMPLETE, fatal protocol error Interrupted By Cleared and Terminated By
3.6.3
Protocol Reset Command
The section considers the issues of the protocol RESET command. The application issues the protocol reset command by writing the RESET command code to the POCCMD field of the Protocol Operation Control Register (POCR). As a result, the PE stops its operation immediately, the FlexRay bus ports put into their idle state, and no more data or status information is sent to the CHI. The lack of PE signals stops all message buffer operations in the CHI. In particular, the message buffers that are currently under internal use remain internally locked. To overcome this message buffer internal lock situation, the application must put the protocol into the POC:default config state. This will release all internal message buffer locks. The following sequence must be executed by the application to put the protocol into the POC:default config state. 1. Repeat sending the Protocol Command FREEZE via Protocol Operation Control Register (POCR), until the freeze bit FRZ in Protocol Status Register 1 (PSR1) is set. 2. Repeat sending the Protocol Command DEFAULT_CONFIG via Protocol Operation Control Register (POCR) , until the freeze bit FRZ bit in Protocol Status Register 1 (PSR1) is clear and the PROTSTATE field in Protocol Status Register 0 (PSR0) is set to DEFAULT_CONFIG.
MFR4300 Data Sheet, Rev. 3 204 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM)
4.1
4.1.1
Introduction
Overview
The Port Integration Module implements the interfaces between the FlexRay IP block, the peripheral modules, and the I/O pins.
4.1.2
Features
The Port Integration Module includes these distinctive features: * Pad control for all functional pads including: -- drive strength enable (DSE), via a control register -- pull enable (PUE), via a control register -- pull select (PUS), via a control register * Pin multiplexing and direction control for reset mode
4.1.3
Modes of Operation
The Port Integration Module can be put into the following modes: * Functional Mode In this mode, the module drives each associated pin and has complete control of the direction of that pin. The drive strength and pullup/pulldown enable are controlled via a set of control registers. * Reset Mode In this mode, the pin configuration is changed for: -- clock output control: CLK_S0 and CLK_S1 -- host interface control: IF_SEL0 and IF_SEL1 The control signals become available on the corresponding pins in reset mode. Refer to Chapter 6, "Clocks and Reset Generator (CRG)" for reset mode details. This is a high level description only; detailed descriptions of operating modes are contained in later sections.
4.2
External Signal Description
For detailed descriptions of particular pins and signals, refer to Section 2.4, "Signal Descriptions".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 205
Port Integration Module (PIM)
4.2.1
Functional Mode
Table 4-1. Pin Functions (Functional Mode)
Name Function Direction Special Configuration1
Host Interface A[6:1]/XADDR[14:19] AMI address bus / HCS12 expanded address lines. A1-LSB of the AMI address bus, XADDR14-LSB of the HCS12 expanded address lines AMI address bus AMI read output enable signal / HCS12 address select input AMI address bus / HCS12 address select inputs AMI byte select / Debug strobe point AMI data bus / HCS12 multiplexed address/data bus. D15 is the MSB of the AMI data bus, PB0 is the LSB of the HCS12 address/data bus AMI data bus / HCS12 multiplexed address/data bus. D0 is the LSB of the AMI data bus, PA7 is the MSB of the HCS12 address/data bus AMI chip select signal / HCS12 low-byte strobe signal AMI write enable signal/ HCS12 read/write select signal AMI address bus/ HCS12 clock inputHCS12 interface, clock input Input PU/PD
A[7:9] OE#/ACS0 A[12:11]/ACS[2:1] BSEL[1:0]#/DBG[0:1] D[15:8]/PB[0:7]
Input Input Input Input/Output Input/Output
PU/PD PU/PD PU/PD DC/PU/PD DC/PU/PD
D[7:0]/PA[0:7]
Input/Output
DC/PU/PD
CE#/LSTRB WE#/RW_CC# A10/ECLK_CC
Input Input Input
PU/PD PU/PD PU/PD
Physical Layer Interface RXD_BG[2:1] TXEN[2:1]# TXD_BG[1:2]/IF_SEL[1:0] PHY Data receiver input Transmit enable for PHY PHY Data transmitter output / Host interface select Input Output Input/Output PU/PD DC DC
Clock Interface CHICLK_CC CLKOUT External CHI clock input selectable Controller clock output selectable between disabled, 4/10/40 MHz Input Output DC
Other RESET# INT_CC# TEST Hardware reset input Controller interrupt output Factory Test mode select -- must be tied to logic low in application Input Output Input DC/OD PD
MFR4300 Data Sheet, Rev. 3 206 Freescale Semiconductor
Table 4-1. Pin Functions (Functional Mode) (Continued)
Name DBG[3:2]/CLK_S[1:0] Function Debug strobe point / External CHI clock input select Oscillator EXTAL/CC_CLK XTAL
1
Direction Output
Special Configuration1 DC
Crystal driver / External clock Crystal driver
Input Input
-
Acronyms: PC - (Pullup/pulldown Controlled) Register controlled internal weak pullup/pulldown for a pin in the input mode PD - (Pulldown) Internal weak pulldown for a pin in the input mode DC - (Drive strength Controlled) Register controlled drive strength for a pin in the output mode
4.2.2
Reset Mode
This pin configuration is enabled in reset mode only. Refer to Chapter 6, "Clocks and Reset Generator (CRG)" for reset mode details. When the device is in reset mode, the corresponding pads go into input mode with pulldown enabled.
Table 4-2. Pin Functions (Reset Mode)
Name TXD_BG[1:2]/IF_SEL[1:0] DBG[3:2]/CLK_S[1:0]
1
Direction Input Input
Special Configuration1 PD PD
Acronyms: PD - (Pulldown) Internal weak pulldown for a pin in the input mode
4.3
PIM Memory Map and Registers
This section provides a detailed description of all registers in the Port Integration Module. Only 16-bit reads and 8-bit and 16-bit writes are allowed to all registers.
Table 4-3. Port Integration Module Memory Map
Address 0x00F0 0x00F2 0x00F4 0x00F6 0x00F8 0x00FA 0x00FC 0x00FE Use Part ID Register (PIDR) ASIC Version Number Register (AVNR) Host Interface Pins Drive Strength Register (HIPDSR) Physical Layer Pins Drive Strength Register (PLPDSR) Host Interface Pins Pullup/pulldown Enable Register (HIPPER) Host Interface Pins Pullup/pulldown Control Register (HIPPCR) Physical Layer Pins Pullup/pulldown Enable Register (PLPPER) Physical Layer Pins Pullup/pulldown Control Register (PLPPCR) Access R R R/W R/W R/W R/W R/W R/W
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 207
Port Integration Module (PIM)
4.3.1
4.3.1.1
15
Port Integration Module Registers
Part ID Register (PIDR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address in MFR4300 = 0x00F0 R W Reset 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Figure 4-1. Part ID Register (PIDR)
This register provides the part ID (`4300') in binary coded decimal.
4.3.1.2
15
ASIC Version Number Register (AVNR)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address in MFR4300 = 0x00F2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 4-2. ASIC Version Number Register (AVNR)
This register provides the ASIC version number (`0000') in binary coded decimal.
4.3.1.3
15
Host Interface Pins Drive Strength Register (HIPDSR)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00F4 R W 0 0 0 0 0 0 0 0 0 0 0 0
D[0:1 5]/ CLKO DBG[ INT_ PA[0: UT 3:2] CC# 7]/PB[ 0:7] 1 1 1 1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-3. Host Interface Pins Drive Strength Register (HIPDSR)
This register controls the drive strength of the host interface, interrupt, debug, and output clock pins.
Table 4-4. HIPDSR Field Descriptions Field
0 D[0:15]/ PA[0:7]/ PB[0:7] 1 INT_CC#
Description
Host interface output data drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Interrupt output drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full
MFR4300 Data Sheet, Rev. 3 208 Freescale Semiconductor
Table 4-4. HIPDSR Field Descriptions (Continued) Field
2 DBG[3:2] 3 CLKOUT
Description
Debug output (bits 3 and 2 only) drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Output clock drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full
4.3.1.4
15
Physical Layer Pins Drive Strength Register (PLPDSR)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00F6 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TXD_ TXD_ TXEN TXEN BG2 BG1 2# 1# 1 1 1 1
Figure 4-4. Physical Layer Pins Drive Strength Register (PLPDSR)
This register controls the drive strength of the FlexRay physical layer pins.
Table 4-5. PLPDSR Field Descriptions Field
0 TXEN1# 1 TXEN2# 2 TXD_BG1 3 TXD_BG2
Description
Transmit enable (channel A) output drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Transmit enable (channel B) output drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Transmit data (channel A) output drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full Transmit data (channel B) output drive strength control 0 Pin drive strength is reduced to 1/3 of full strength 1 Pin drive strength is full
4.3.1.5
15
Host Interface Pins Pullup/pulldown Enable Register (HIPPER)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00F8 R W 0 0
D[0:1 WE#/ 5]/ A6/ A5/ A4/ A3/ A2/ A1/ CE#/L A12/A A11/A OE#/ BSEL[ A[10: RW_ PA[0: XADD XADD XADD XADD XADD XADD STRB CS2 CS1 ACS0 1:0]# 7] CC# 7]/PB[ R14 R15 R16 R17 R18 R19 0:7] 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset
0
0
Figure 4-5. Host Interface Pins Pullup/pulldown Enable Register (HIPPER)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 209
Port Integration Module (PIM)
This register enables/disables the pullups/pulldowns of the host interface pins.
Table 4-6. HIPPER Field Descriptions Field
0 A1/ XADDR19 A2/ XADDR18 2 A3/ XADDR17 A4/ XADDR16 4 A5/ XADDR15 5 A6/ XADDR14 6 A[10:7]
3 1
Description
AMI address bit 1 / HCS12 expanded address bit 19 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 2 / HCS12 expanded address bit 18 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 3 / HCS12 expanded address bit 17 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 4 / HCS12 expanded address bit 16 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 5 / HCS12 expanded address bit 15 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 6 / HCS12 expanded address bit 14 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bits 7 through 10 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled
NOTE The pullup/pulldown for input A10/ECLK_CC is enabled only when the AMI interface is selected.
7 BSEL[1:0]# 8 OE#/ ACS0 9 A11/ ACS1 10 A12/ ACS2 11 D[0:15]/ PA[0:7]/ PB[0:7] AMI byte select pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI output enable / HCS12 address select bit 0 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 11 / HCS12 address select bit 1 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled AMI address bit 12 / HCS12 address select bit 2 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled Host interface input data pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled
MFR4300 Data Sheet, Rev. 3 210 Freescale Semiconductor
Table 4-6. HIPPER Field Descriptions (Continued) Field Description
12 AMI chip enable / HCS12 low-byte strobe pullup/pulldown enable CE#/LSTRB 0 pullup/pulldown disabled 1 pullup/pulldown enabled 13 AMI write enable / HCS12 read/write select pullup/pulldown enable WE#/RW_C 0 pullup/pulldown disabled C# 1 pullup/pulldown enabled
4.3.1.6
15
Host Interface Pins Pullup/pulldown Control Register (HIPPCR)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00FA R W 0 0
D[0:1 WE#/ 5]/ A6/ A5/ A4/ A3/ A2/ A1/ CE#/L A12/A A11/A OE#/ BSEL[ A[10: RW_ PA[0: XADD XADD XADD XADD XADD XADD STRB CS2 CS1 ACS0 1:0]# 7] CC# 7]/PB[ R14 R15 R16 R17 R18 R19 0:7] 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset
0
0
Figure 4-6. Host Interface Pins Pullup/pulldown Control Register (HIPPCR)
This register enables/disables the pullups/pulldowns of the host interface pins.
Table 4-7. HIPPCR Field Descriptions Field
0 A1/ XADDR19 A2/ XADDR18 2 A3/ XADDR17 A4/ XADDR16 4 A5/ XADDR15 5 A6/ XADDR14 6 A[10:7]
3 1
Description
AMI address bit 1 / HCS12 expanded address bit 19 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 2 / HCS12 expanded address bit 18 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 3 / HCS12 expanded address bit 17 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 4 / HCS12 expanded address bit 16 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 5 / HCS12 expanded address bit 15 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 6 / HCS12 expanded address bit 14 pullup/pulldown control 0 pulldown 1 pullup AMI address bits 7 through 10 pullup/pulldown control 0 pulldown 1 pullup
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 211
Port Integration Module (PIM)
Table 4-7. HIPPCR Field Descriptions (Continued) Field
7 BSEL[1:0]# 8 OE#/ACS0 9 A11/ACS1 10 A12/ACS2 AMI byte select pullup/pulldown control 0 pulldown 1 pullup AMI output enable / HCS12 address select bit 0 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 11 / HCS12 address select bit 1 pullup/pulldown control 0 pulldown 1 pullup AMI address bit 12 / HCS12 address select bit 2 pullup/pulldown control 0 pulldown 1 pullup
Description
11 Host interface input data pullup/pulldown control D[0:15]/ 0 pulldown PA[0:7]/PB[0: 1 pullup 7] 12 AMI chip enable / HCS12 low-byte strobe pullup/pulldown control CE#/LSTRB 0 pulldown 1 pullup 13 AMI write enable / HCS12 read/write select pullup/pulldown control WE#/RW_C 0 pulldown C# 1 pullup
4.3.1.7
15
Physical Layer Pins Pullup/pulldown Enable Register (PLPPER)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00FC R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXD_ RXD_ BG2 BG1 0 0
Figure 4-7. Physical Layer Pins Pullup/pulldown Enable Register (PLPPER)
This register enables/disables the pullups/pulldowns of the FlexRay physical layer pins.
Table 4-8. PLPPER Field Descriptions Field
0 RXD_BG1 RXD_BG2
1
Description
Receive data (channel A) pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled Receive data (channel B) pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled
MFR4300 Data Sheet, Rev. 3 212 Freescale Semiconductor
4.3.1.8
15
Physical Layer Pins Pullup/pulldown Control Register (PLPPCR)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00FE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXD_ RXD_ BG2 BG1 0 0
Figure 4-8. Physical Layer Pins Pullup/pulldown Control Register (PLPPCR)
This register enables/disables the pullups/pulldowns of the host interface pins.
Table 4-9. PLPPCR Field Descriptions Field
0 RXD_BG1 RXD_BG2
1
Description
Receive data (channel A) pullup/pulldown control 0 pulldown 1 pullup Receive data (channel B) pullup/pulldown control 0 pulldown 1 pullup
4.4
Functional Description
The Port Integration Module provides the capability to configure all functional I/O pins regarding: * output drive with two selectable drive strengths * Pullup or pulldown * Pin multiplexing and pin configuration constraints for reset mode
4.4.1
Functional Mode
In functional mode, the Port Integration Module controls the functional interface: * Host Interface * Physical Layer Interface * Clock Interface The module provides pullup/pulldown and drive strength control through configuration registers via the IPBus interface. The actual control registers are described in Section 4.3, "PIM Memory Map and Registers".
4.4.2
Reset Mode
See Section 4.2.2, "Reset Mode" and Chapter 6, "Clocks and Reset Generator (CRG)" for reset mode details.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 213
Port Integration Module (PIM)
MFR4300 Data Sheet, Rev. 3 214 Freescale Semiconductor
Chapter 5 Dual Output Voltage Regulator (VREG3V3V2)
5.1 Introduction
The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical).
5.1.1
Features
The block VREG3V3V2 includes these distinctive features: * Two parallel, linear voltage regulators -- Bandgap reference * Power-on reset (POR) * Low-voltage reset (LVR)
5.1.2
Modes of Operation
VREG3V3V2 can operate in two modes on MFR4300: * Full-performance mode (FPM) The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing capability at both outputs. Features LVR (low-voltage reset) and POR (power-on reset) are available. * Shutdown mode Controlled by VDDR. This mode is characterized by minimum power consumption. The regulator outputs are in a high impedance state; only the POR feature is available, and LVR is disabled. This mode must be used to disable the chip internal regulator VREG3V3V2, i.e., to bypass the VREG3V3V2 to use external supplies.
5.1.3
Block Diagram
Figure 5-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 215
Dual Output Voltage Regulator (VREG3V3V2)
VDDR VDDA VSSA REG VSSR
REG2
VDDOSC VSSOSC
REG1
VDD
LVR
LVR
POR
POR
VSS
CTRL REG: Regulator Core CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN
Figure 5-1. VREG3V3 Block Diagram
MFR4300 Data Sheet, Rev. 3 216 Freescale Semiconductor
Dual Output Voltage Regulator (VREG3V3V2)
5.2
External Signal Description
Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 5-1 shows all signals of VREG3V3V2 associated with pins.
Table 5-1. VREG3V3V2 -- Signal Properties
Name VDDR VSSR VDDA VSSA VDD VSS VDDOSC VSSOSC Port -- -- -- -- -- -- -- -- Function VREG3V3V2 power input (positive supply) VREG3V3V2 power input (ground) VREG3V3V2 quiet input (positive supply) VREG3V3V2 quiet input (ground) VREG3V3V2 primary output (positive supply) VREG3V3V2 primary output (ground) VREG3V3V2 secondary output (positive supply) VREG3V3V2 secondary output (ground) Reset State -- -- -- -- -- -- -- -- Pullup -- -- -- -- -- -- -- --
NOTE Check device overview chapter for connectivity of the signals.
5.2.1
VDDR, VSSR -- Regulator Power Input
Signal VDDR is the power input of VREG3V3V2. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR can smoothen ripple on VDDR. For entering shutdown mode, pin VDDR must be tied to ground. In that case, VDD/VSS and VDDOSC/VSSOSC must be provided externally.
5.2.2
VDDA, VSSA -- Regulator Reference Supply
Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 217
Dual Output Voltage Regulator (VREG3V3V2)
5.2.3
VDD, VSS -- Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDD/VSS can replace the voltage regulator.
5.2.4
VDDOSC, VSSOSC -- Regulator Output2 (OSC)
Signals VDDOSC/VSSOSC are the secondary outputs of VREG3V3V2 that provide the power supply for the oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDDOSC/VSSOSC can replace the voltage regulator.
5.3
Functional Description
Block VREG3V3V2 is a voltage regulator as depicted in Figure 5-1. The regulator functional elements are the regulator core (REG), a power-on reset module (POR) and a low-voltage reset module (LVR). There is also the regulator control block (CTRL) which manages the operating modes of VREG3V3V2.
5.3.1
REG -- Regulator Core
VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2. The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a voltage clamp in reduced-power mode. All load currents flow from input VDDR to VSS or VSSOSC, the reference circuits are connected to VDDA and VSSA.
5.3.2
Full-performance Mode
In full-performance mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver.
5.3.3
POR -- Power On Reset
This functional block monitors output VDD. If VDD is below VPORD, signal POR is high; if it exceeds VPORD, the signal goes low. The transition to low forces the CPU into the power-on sequence. Due to its role during chip power-up, this module must be active in all operating modes of VREG3V3V2.
MFR4300 Data Sheet, Rev. 3 218 Freescale Semiconductor
Dual Output Voltage Regulator (VREG3V3V2)
5.3.4
LVR -- Low Voltage Reset
Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal LVR asserts and when rising above the deassertion level (VLVRD) signal LVR deasserts again. The LVR function is available only in full-performance mode.
5.3.5
CTRL -- Regulator Control
This part contains digital functionality needed to control the operating modes.
5.4
Resets
This subsection describes how VREG3V3V2 controls the reset of the CC. The reset values of registers and signals are provided in Section 3.3, "Memory Map and Register Description". Possible reset sources are listed in Table 5-2.
Table 5-2. VREG3V3V2 -- Reset Sources
Reset Source Power-on reset Low-voltage reset Always active Always active Local Enable
5.4.1
Power On Reset
During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset, is kept high until VDD exceeds VPORD. Then POR becomes low and the reset generator of the device continues the start-up sequence.
5.4.2
Low Voltage Reset
For information on low-voltage reset see Section 5.3.4, "LVR -- Low Voltage Reset".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 219
Dual Output Voltage Regulator (VREG3V3V2)
MFR4300 Data Sheet, Rev. 3 220 Freescale Semiconductor
Chapter 6 Clocks and Reset Generator (CRG)
6.1
6.1.1
Introduction
Overview
This document describes the CRG operation in functional mode and only those aspects of it which are useful users. Additional topics as system clock generation or functionality while the CRG is in another operational modes are out of the scope of this documentation.
6.1.2
Features
The CRG includes the following main features: * System reset generation from power-on and external reset events * System reset generation from low voltage reset event * Controllable system reset generation under low quality clock situations (clock monitor) * System reset indication * Host interface selection * Control signals selection for CLKOUT clock output * System clocks generation
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 221
Clocks and Reset Generator (CRG)
6.2
MFR4300 Relevant Pins for the CRG
Table 6-1. MFR4300 Relevant Pins for the CRG
Pin Name1 In/Out Pin type2,3 I/O I I/O I O I I/O I I DC/PD DC OD/DC PD DC/PD Functional Description PHY Data transmitter output / Host interface select External CHI clock input - selectable Controller clock output-selectable between disabled, 4/10/40 MHz/ Test mode selection for production testing only Hardware reset input Controller interrupt output Factory Test mode select- should be tied to logic low in application Debug strobe point / Output clock select Crystal driver / External clock pin Crystal driver pin
Table 6-1 describes the MFR4300 pins relevant for the CRG block.
TXD_BG[1:2]/IF_SEL[1:0] CHICLK_CC CLKOUT/TM0 RESET# INT_CC# TEST DBG[3:2]/CLK_S[1:0] EXTAL/CLK_CC XTAL
1 2
# - signal is active-low Acronyms: PC - (Pullup/pulldown Controlled) Register controlled internal weak pullup/pulldown for a pin in the input mode PD - (Pulldown) Internal weak pulldown for a pin in the input mode DC - (Drive strength Controlled) Register controlled drive strength for a pin in the output mode Z - Tristated pin 3 Reset state: All pins with the PC option - pullup/pulldown is disabled, all pins with the DC option - have full drive strength
6.3
6.3.1
CRG Registers
Detection Enable Register (DER)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13
Address in MFR4300 = 0x00E0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
CMIE 0
Figure 6-1. Detection Enable Register (DER) Table 6-2. DER Field Descriptions Field
0 CMIE Clock Monitor Mechanism Enable 0 Range filter disabled 1 Range filter enabled
Description
MFR4300 Data Sheet, Rev. 3 222 Freescale Semiconductor
Clocks and Reset Generator (CRG)
NOTE After reset, the clock monitor mechanism is disabled.
6.3.2
15
Clock and Reset Status Register (CRSR)
Write: Any Time
12 11 10 9 8 7 6 5 4 3 2 1 0 14 13
Address in MFR4300 = 0x00E2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDCV ECS 0 0 0 0
ERIF 0
PRIF CMIF 0 0
LVIF 0
Figure 6-2. Clock and Reset Status Register (CRSR) Table 6-3. CRSR Field Descriptions Field
0 LVIF 1 CMIF 2 PRIF 3 ERIF 8 ECS 10-9 CDCV
Description
Low Voltage Reset Interrupt Flag -- set when a low-voltage reset has occurred. Cleared when writing a 1. Writing 0 has no effect. Clock Monitor Reset Interrupt Flag -- set when a clock-monitor reset has occurred. Cleared when writing a 1. Writing 0 has no effect. Note: If LVIF bit or PRIF bit is set to 1 then the CMIF bit value is 0. Power-on Reset Interrupt Flag -- set when a power-on reset has occurred. Cleared when writing a 1. Writing 0 has no effect. External Reset Interrupt Flag -- set when a external reset has occurred. Cleared when writing a 1. Writing 0 has no effect. Note: If LVIF bit or PRIF bit is set to 1 then the ERIF bit value is "0". CHI and host interface Clock Source 0 CHI and host interface are clocked by EXTAL/CLK_CC 1 CHI and host interface are clocked by CHICLK_CC CLKOUT Division Control Value -- contains sampled value of CLK_S[1:0]. The CRG writes this value after a power-on, low-voltage or clock monitor reset, according to the values sampled on the CLK_S[1:0] pins. See Table 2-5 for coding.
NOTE On a power-on or low-voltage reset, CMIF and PRIF are both cleared to "0".
6.4
6.4.1
Functional Description
Reset Generation
The CRG will provide a system reset in any of the following events: power-on, low-voltage or clock monitor failure detected, low level detected at the RESET# pin. Entry into reset is asynchronous and does not require a clock. However, the MFR4300 cannot sequence out of reset in Functional Mode without a system clock. Table 6-4 depicts reset sources priorities. The CRG scans, during different periods depending on the origin of the reset source, the interface type, the AMI clock source and the CLKOUT mode selection pins: IF_SEL[1:0] and CLK_S[1:0].
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 223
Clocks and Reset Generator (CRG)
Table 6-4. CRG Reset Sources Priorities
Reset Source Power-on Reset Low voltage or Clock Monitor Failure (if enabled) Reset External Reset Block to Reset Whole device Whole device Whole device High Low Priority
NOTE Once the CRG had started a reset procedure it will not abandon it unless a reset event with more priority was detected. The reset procedure which has the same priority, as currently running one, stops the previous procedure and gets executed.
6.4.1.1
Power-on Reset
When the power-on reset signal is asserted the CRG asserts the system reset signal. The CRG will deassert synchronously the system reset signal approximately 16420 EXTAL/CLK_CC clock periods after the deassertion of the power-on reset signal. The CRG asserts the INT_CC# interrupt line and the power-on reset interrupt flag, CRSR.PRIF, on the rising edge of the power-on reset signal. NOTE The CRG deasserts the INT_CC# signal when CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are "0". Figure 6-3 illustrates the power-on reset situation.
MFR4300 Data Sheet, Rev. 3 224 Freescale Semiconductor
Clocks and Reset Generator (CRG)
VDD
power-on reset
CRSR.PRIF ~16420 EXTAL/CLK_CC periods
system reset
INT_CC#
Figure 6-3. CRG Power On Reset
6.4.1.2
Low Voltage and Clock Monitor Reset
When the low voltage reset or clock monitor failure signal is asserted the CRG asserts the system reset signal. The CRG will deassert synchronously the system reset signal approximately 16420 EXTAL/CLK_CC clock periods after the deassertion of the low voltage reset or clock monitor failure signal. The CRG asserts the INT_CC# interrupt line and the low voltage reset interrupt flag, CRSR.LVIF, on the rising edge of the low voltage reset signal. The CRG asserts the INT_CC# interrupt line and the clock monitor failure interrupt flag, CRSR.CMIF, on the rising edge of the clock monitor failure signal. NOTE The CRG deasserts the INT_CC# signal when CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are "0". Figure 6-4 and Figure 6-5 show the operations performed by the CRG when a low voltage reset or a clock monitor failure signal occur.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 225
Clocks and Reset Generator (CRG)
low voltage reset
CRSR.LVIF
~16420 EXTAL/CLK_CC periods
system reset
INT_CC#
Figure 6-4. Low Voltage Reset
clock monitor failure (if enabled)
CRSR.CMIF
~16420 EXTAL/CLK_CC periods
system reset
INT_CC#
Figure 6-5. Clock Monitor Failure Reset
6.4.1.3
External Reset
When the RESET# signal is asserted the CRG asserts the system reset signal. The CRG will deassert the system reset signal approximately 70 EXTAL/CLK_CC clock periods after the deassertion of the RESET#. The CRG asserts the INT_CC# interrupt line and the external reset interrupt flag, CRSR.ERIF, on the assertion of the RESET# signal. NOTE The CRG deasserts the INT_CC# signal when CRSR.PRIF, CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are "0". Figure 6-6 illustrates an external reset scheme.
MFR4300 Data Sheet, Rev. 3 226 Freescale Semiconductor
Clocks and Reset Generator (CRG)
RESET#
CRSR.ERIF
~70 EXTAL/CLK_CC periods
system reset
INT_CC#
Figure 6-6. External Reset
6.4.2
Interface Selection
The interface mode selection is done when the TXD_BG[1:2]/IF_SEL[1:0] pins are in the IF_SEL[1:0] mode. In the TXD_BG[1:2] modes the pads are outputs from the MFR4300 device. NOTE The PIM block selects the TXD_BG[1:2]/IF_SEL[1:0] pads modes based on the system reset signal.
6.4.2.1
Interface and AMI Clock Selection
The interface selection is made upon the levels on the bus signal IF_SEL[1:0] while a power-on, low voltage, clock monitor or external reset process is ongoing. The CRG latches the IF_SEL[1:0] during the latching window as presented on Figure 6-7 and Figure 6-8.
Latching window power-on reset or low voltage reset or clock monitor failure IF_SEL[1:0] ~16380 EXTAL/CLK_CC periods ~16410 EXTAL/CLK_CC periods Figure 6-7. Interface Selection during Power-on or Low Voltage Reset or Clock Monitor Failure
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 227
Clocks and Reset Generator (CRG)
Latching window RESET#
IF_SEL[0;1] ~30 EXTAL/CLK_CC periods ~60 EXTAL/CLK_CC periods Figure 6-8. Interface Selection during External Reset
Next table shows the interface selection encoding provided by the CRSR.ECS bit:
Table 6-5. IF_SEL[1:0] Encoding by CRSR.ECS
IF_SEL1 1 0 1 IF_SEL0 0 1 1 CRSR.ECS 0 0 1
If, after the evaluation, the IF_SEL[1:0] are both high, the CRG sets to 1 the CRSR.ECS bit; otherwise the CRG resets that bit.
6.4.3
CLKOUT Mode Selection and Control
The CLKOUT mode selection is done when the DBG[3:2]/CLK_S[1:0] pins are in the CLK_S[1:0] mode. In the DBG[3:2] modes the pads are outputs from the MFR4300 device. NOTE The PIM block selects the DBG[3:2]/CLK_S[1:0] pads modes based on the system reset signal. The CLKOUT mode selection is made upon the levels of the CLK_S[1:0] signals in the latching window while a power-on, low voltage, clock monitor or external reset process is ongoing. The CRG latches the CLK_S[1:0] signal values during the latching window as presented on Figure 6-9, Figure 6-10 and Figure 6-11. The latched values are indicated in the CRSR.CDCV field.
MFR4300 Data Sheet, Rev. 3 228 Freescale Semiconductor
Clocks and Reset Generator (CRG)
low voltage reset or clock monitor failure
Latching window
CLK_S[1:0] ~16380 EXTAL/CLK_CC periods ~16410 EXTAL/CLK_CC periods
CLKOUT
~16420 EXTAL/CLK_CC periods
system reset Figure 6-9. CLKOUT Mode Selection and Control during Low-voltage Reset or Clock Monitor Failure
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 229
Clocks and Reset Generator (CRG)
Latching window RESET#
CLK_S[1:0] ~30 EXTAL/CLK_CC periods ~60 EXTAL/CLK_CC periods
CLKOUT
~70 EXTAL/CLK_CC periods
system reset Figure 6-10. CLKOUT Mode Selection and Control during External Reset
MFR4300 Data Sheet, Rev. 3 230 Freescale Semiconductor
Clocks and Reset Generator (CRG)
power-on reset
Latching window
CLK_S[1:0] ~16380 EXTAL/CLK_CC periods ~16410 EXTAL/CLK_CC periods
CLKOUT
~16420 EXTAL/CLK_CC periods
system reset Figure 6-11. CLKOUT Mode Selection and Control during Power-on Reset
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 231
Clocks and Reset Generator (CRG)
MFR4300 Data Sheet, Rev. 3 232 Freescale Semiconductor
Chapter 7 Oscillator (FLEXRAY)
7.1 Introduction
The FLEXRAY module provides one oscillator concept: * A robust full swing Pierce oscillator with the possibility to feed in an external square wave
7.1.1
Features
The Pierce oscillator provides the following features: * Wide high frequency operation range * No DC voltage applied across the crystal * Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility * Fast start up Common features: * Clock monitor (CM) * Operation from the VDDOSC 2.5 V (nominal) supply rail
7.1.2
Modes of Operation
One mode of operation exists: * Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments
7.2
External Signal Description
This section lists and describes the signals that connect off chip.
7.2.1
VDDOSC and VSSOSC -- OSC Operating Voltage, OSC Ground
These pins provide the operating voltage (VDDOSC) and ground (VSSOSC) for the FLEXRAY circuitry. This allows the supply voltage to the FLEXRAY to be independently bypassed.
7.2.2
EXTAL and XTAL -- Clock/Crystal Source Pins
These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 233
Oscillator (FLEXRAY)
XTAL is the output of the crystal oscillator amplifier. All internal system clocks are derived from the EXTAL input frequency. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The Crystal circuit is changed from standard. The Pierce circuit is not suited for overtone resonators and crystals without a careful component selection. For more information, see the EXTAL pin description in Chapter 2.
MFR4300 Data Sheet, Rev. 3 234 Freescale Semiconductor
Oscillator (FLEXRAY)
7.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the FLEXRAY module.
7.4
Functional Description
The FLEXRAY block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal, OSCCLK, becomes the internal reference clock. To improve noise immunity, the oscillator is powered by the VDDOSC and VSSOSC power supply pins.
7.4.1
Clock Monitor (CM)
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without a clock. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates a failure which asserts self clock mode or generates a system reset depending on the state of the SCME bit. If the clock monitor is disabled or the presence of clocks is detected, no failure is indicated. The clock monitor function is enabled/disabled by the CME control bit, described in Chapter 6, "Clocks and Reset Generator (CRG)".
7.5
Resets
FLEXRAY contains a clock monitor, which can trigger a reset. The control bits and status bits for the clock monitor are described in Chapter 6, "Clocks and Reset Generator (CRG)".
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 235
Oscillator (FLEXRAY)
MFR4300 Data Sheet, Rev. 3 236 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1 General
NOTE The electrical characteristics given in this appendix are preliminary and must be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. NOTE The part is specified and tested over the 5 V and 3.3 V ranges. For the intermediate range, generally the electrical specifications for the 3.3 V range apply, but the part is not tested in production test in the intermediate range. This appendix provides the most accurate electrical information for the MFR4300 device available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. The following classifications are used and the parameters are tagged accordingly in the column labeled `C' in the parameter tables, where appropriate. P: C: T: Parameters that are guaranteed during production testing on each individual device. Parameters that are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Parameters that are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Parameters that are derived mainly from simulations.
D:
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 237
Electrical Characteristics
A.1.2
Power Supply
The MFR4300 uses several pins to supply power to the I/O pins, oscillator and the digital core. The VDDA, VSSA pair supplies the internal voltage regulator. The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD2_5 and VSS2_5 are the supply pins for the digital logic, VDDOSC, VSSOSC supply the oscillator. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context, VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD2_5 and VDDOSC, VSS is used for VSS2_5 and VSSOSC. IDD is used for the current flowing into VDD2_5.
A.1.3
Pins
There are four groups of functional pins.
A.1.3.1
3.3V I/O pins
Those I/O pins have a nominal level of 3.3V. This class of pins is comprised of all I/O pins (all MFR4300 pins excluding EXTAL, XTAL and all power supply pins).The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the input-only pins the output drivers are disabled permanently.
A.1.3.2
Oscillator
The pins EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDOSC.
A.1.3.3
VDDR
This pin is used to enable the on chip voltage regulator.
MFR4300 Data Sheet, Rev. 3 238 Freescale Semiconductor
Electrical Characteristics
A.1.4
Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the CC is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5
Absolute Maximum Ratings
CAUTION Long-term exposure to absolute maximum ratings may affect device reliability, and permanent damage may occur if operate exceeding the rating. The device should be operated under recommended operating condition.
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1. Absolute Maximum Ratings
Num 1 2 3 4 5 6 7 8 9 10 11 12 Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 1 Oscillator Supply Voltage
1
Symbol VDD5 VDD VDDOSC VDDX VSSX VIN VILV ID IDL TA TJ Tstg
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -40 -40 - 65
Max 6.5 3.0 3.0 0.3 0.3 6.5 3.0 +25 +25 +125 +150 +155
Unit V V V V V V V mA mA
o o
Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage2 EXTAL, XTAL inputs Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for EXTAL, XTAL4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
C C
C
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 239
Electrical Characteristics
1
The device contains an internal voltage regulator to generate the logic and OSC supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2 AC over or undershoots for 2V beyond the supply if limited to 20ns length are allowed. 3 All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4 Those pins are internally clamped to VSSOSC and VDDOSC.
A.1.6
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table A-2. ESD and Latch-up Test Conditions
Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin positive negative Machine Series Resistance Storage Capacitance Number of Pulse per pin positive negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C -- Value 1500 100 -- 3 3 0 200 -- 3 3 -2.5 7.5 V V pF Unit pF
R1 C --
-- --
Table A-3. ESD and Latch-up Protection Characteristics
Num C 1 2 3 4 Rating Symbol VHBM VMM VCDM ILAT +100 -100 ILAT +200 -200 -- -- mA Min 2000 200 500 Max -- -- -- Unit V V V mA
T Human Body Model (HBM) T Machine Model (MM) T Charge Device Model (CDM) T Latch-up Current at TA = 125C positive negative T Latch-up Current at TA = 27C positive negative
5
MFR4300 Data Sheet, Rev. 3 240 Freescale Semiconductor
Electrical Characteristics
A.1.7
Operating Conditions
This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, "Power Dissipation and Thermal Characteristics".
Table A-4. Operating Conditions
Rating Oscillator and Quartz frequency Quartz overtone Quartz frequency stability at TJ Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA I/O, Regulator and Analog Supply Digital Logic Supply Voltage1 fSTB DVDDX DVSSX VDD5 VDD VDDOSC TJ TJ Symbol fOSC Min -- Typ 40.000 Max 40.000 Unit MHz
Fundamental Frequency -1500 -0.1 -0.1 2.97 2.25 2.25 -40 -40 300 0 0 3.3 2.5 2.5 -- +27 1500 0.1 0.1 5.5 2.75 2.75 +140 +125 ppm V V V V V
oC oC
Oscillator Supply Voltage1 Operating Junction Temperature Range Operating Ambient Temperature Range2
1 2
The device contains an internal voltage regulator to generate the logic and OSC supply out of the I/O supply. Refer to Section A.1.8, "Power Dissipation and Thermal Characteristics" for more information about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D JA ) Eqn. A-1
TJ = Junction Temperature [C] TA = Ambient Temperature [C] PD = Total Chip Power Dissipation [W] JA = Package Thermal Resistance [C/W] The total power dissipation can be calculated from:
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 241
Electrical Characteristics
P D = P INT + P IO
Eqn. A-2
PINT = Chip Internal Power Dissipation [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled
P INT = I DD V DD + I DDOSC V DDOSC + I DDA V DDA Eqn. A-3
P IO =
R
i
DSON
I IOi
2
Eqn. A-4
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid:
V OL R DSON = --------- ; for outputs driven low I OL Eqn. A-5
respectively
V DD5 - V OH R DSON = ----------------------------- ; for outputs driven high I OH Eqn. A-6
2. Internal voltage regulator enabled
P INT = I DDR V DDR + I DDA V DDA Eqn. A-7
IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high.
P IO =
R
i
DSON
I IOi
2
Eqn. A-8
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
MFR4300 Data Sheet, Rev. 3 242 Freescale Semiconductor
Electrical Characteristics
Table A-5. Thermal Package Simulation Details
Num 1 2 3 4 5 6 7
1
Rating Junction to Ambient LQFP64, single sided PCB1,2, Natural Convection Junction to Ambient LQFP64, double sided PCB with 2 internal planes1,3, Natural Convection Junction to Ambient LQFP64 (@200 ft/min), single sided PCB1,3 Junction to Ambient LQFP64 (@200 ft/min), double sided PCB with 2 internal planes1,3 Junction to Board LQFP644 Junction to Case LQFP645 Junction to Package Top LQFP646, Natural Convection
Symbol RJA RJMA RJMA RJMA RJB RJC JT
Value TBD TBD TBD TBD TBD TBD TBD
Unit
o o
C/W C/W C/W C/W C/W C/W C/W
o o
o o o
2 3 4 5 6
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JEDEC Standard 51-2 with the single layer horizontal PC Board according to EIA/JEDEC Standard 51-3 Per EIA/JEDEC Standard 51-6 with the four layer horizontal PC Board (double-sided PCB with two internal planes) according to EIA/JEDEC Standard 51-7 Thermal resistance between the die and the printed circuit board per EIA/JEDEC Standard 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per EIA/JEDEC Standard 51-2.
A.1.9
I/O Characteristics
This section describes the characteristics of all 3.3V I/O pins. All parameters are not always applicable, e.g. not all pins feature pullup/pulldown resistances.
Table A-6. 5V I/O Characteristics (VDD5 = 5V)
Conditions are shown in Figure A-4, unless otherwise noted. Num 1 C P T 2 P T 3 4 5 C P P Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis High Impedance (Off-state) Leakage Current VIN=VDD or VSS, all input/output and output pins Output High Voltage (pins in output mode) @50% Partial Drive IOH = -2mA Rating Symbol VIH VIH VIL VIL VHYS IIN VOH Min 0.65*VDD5 -- -- VSS5 -0.3 -- -2.5 VDD5 -0.8 Typ -- -- -- -- 250 -- -- Max -- VDD5+0.3 0.35*VDD5 -- -- +2.5 -- Unit V V V V mV uA V
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 243
Electrical Characteristics
Table A-6. 5V I/O Characteristics (VDD5 = 5V) (Continued)
Conditions are shown in Figure A-4, unless otherwise noted. Num 6 7 8 9 10 11 12 13 14 C P P P P P P P d T Rating Output High Voltage (pins in output mode) @100% Full Drive IOH = -10mA Output Low Voltage (pins in output mode) @50% Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) @100% Full Drive IOL = +10mA Internal Pullup Device Current, tested at VIL Max Internal Pullup Device Current, tested at VIH Min. Internal Pulldown Device Current, tested at VIH Min. Internal Pulldown Device Current, tested at VIL Max Input Capacitance (input, input/output pins) Injection Current1 Single Pin Limit Total Device Limit. Sum of all injected currents 15 P Load Capacitance 50% Partial Drive 100% Full Drive IICS IICP CL -2.5 -25 -- -- -- -- 25 50 2.5 25 pF Symbol VOH VOL VOL IPUL IPUH IPDH IPDL CIN Min VDD5 --0.8 -- -- -- -10 -- 10 -- Typ -- -- -- -- -- -- -- 7 Max -- 0.8 0.8 -130 -- 130 -- -- Unit V V V uA uA uA uA pF mA
1
Refer to Section A.1.4, "Current Injection", for more information.
Table A-7. 3.3V I/O Characteristics (VDD5 = 3.3V)
Conditions are VDDX=3.3V 10% Temperature from -40oC to +140oC, unless otherwise noted Num 1 C P T 2 P T 3 4 5 C P P Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis High Impedance (Off-state) Leakage Current VIN=VDD or VSS, all input/output and output pins Output High Voltage (pins in output mode) @50% Partial Drive IOH = -0.75mA Rating Symbol VIH VIH VIL VIL VHYS IIN VOH Min 0.65*VDD5 -- -- VSS5 -0.3 -- -2.5 VDD5 -0.4 Typ -- -- -- -- 250 -- -- Max -- VDD5+0.3 0.35*VDD5 -- -- +2.5 -- Unit V V V V mV uA V
MFR4300 Data Sheet, Rev. 3 244 Freescale Semiconductor
Electrical Characteristics
Table A-7. 3.3V I/O Characteristics (VDD5 = 3.3V) (Continued)
Conditions are VDDX=3.3V 10% Temperature from -40oC to +140oC, unless otherwise noted Num 6 7 8 9 10 11 12 13 14 C P P P P P P P D T Rating Output High Voltage (pins in output mode) @100% Full Drive IOH = -4.5mA Output Low Voltage (pins in output mode) @50% Partial Drive IOL = +0.9mA Output Low Voltage (pins in output mode) @100% Full Drive IOL = +5.5mA Internal Pullup Device Current, tested at VIL Max Internal Pullup Device Current, tested at VIH Min. Internal Pulldown Device Current, tested at VIH Min. Internal Pulldown Device Current, tested at VIL Max Input Capacitance (input, input/output pins) Injection Current1 Single Pin Limit Total Device Limit. Sum of all injected currents 15 P Load Capacitance 50% Partial Drive 100% Full Drive IICS IICP CL -2.5 -25 -- -- -- -- 25 50 2.5 25 pF Symbol VOH VOL VOL IPUL IPUH IPDH IPDL CIN Min VDD5 -0.4 -- -- -- -6 -- 6 -- Typ -- -- -- -- -- -- -- 7 Max -- 0.4 0.4 -60 -- 60 -- -- Unit V V V uA uA uA uA pF mA
1
Refer to Section A.1.4, "Current Injection" for more information.
A.1.10
Supply Currents
All measurements are done without output loads. Unless otherwise noted, the currents are measured with internal voltage regulator enabled and a 40 MHz oscillator, in standard Pierce mode. Production testing is performed using a square wave signal at the EXTAL input.
Table A-8. Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 Rating -40C 25C 140C Symbol IDD5 Min -- -- -- Typ -- -- -- Max TBD TBD TBD Unit mA
P Run supply currents Internal regulator enabled
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 245
Electrical Characteristics
A.2
A.2.1
Voltage Regulator (VREG)
Operating Conditions
Table A-9. Voltage Regulator -- Operating Conditions
Conditions are shown in Table A-4 unless otherwise noted Num 1 2 3 C P P P Characteristic Input Voltages Regulator Current Shutdown Mode Output Voltage Core Full Performance Mode Shutdown Mode Output Voltage OSC Full Performance Mode Shutdown Mode Low Voltage Reset3 Assert Level Power-on Reset4 Assert Level Deassert Level Symbol VVDDR,A IREG Min 2.97 -- Typical -- TBD Max 5.5 40 Unit V A
VDD
2.45 -- 2.35 -- 2.25 0.97 --
2.5 --1 2.5 --2 -- -- --
2.75 -- 2.75 -- -- -- 2.07
V V V V V V V
4
P
VDDOSC
5 6
P C
VLVRA VPORA VPORD
1 2
High Impedance Output High Impedance Output 3 Monitors VDD, always active 4 Monitors VDD, always active
MFR4300 Data Sheet, Rev. 3 246 Freescale Semiconductor
Electrical Characteristics
A.2.2
Chip Power-up and Voltage Drops
Voltage regulator sub modules POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1. V
VDD
VLVRD VLVRA VPORD
t
POR
LVR
Figure A-1. Voltage Regulator -- Chip Power-up and Voltage Drops (not scaled)
A.2.3
A.2.3.1
Output Loads
Resistive Loads
On-chip voltage regulator intended to supply the internal logic and oscillator circuits allows no external DC loads.
A.2.3.2
Capacitive Loads
Table A-10. Voltage Regulator Recommended Capacitive Loads
The capacitive loads are specified in Figure A-10. Ceramic capacitors with X7R dielectricum are required
Num 1 3
Characteristic VDD external capacitive load VDDOSC external capacitive load
Symbol CDDext CDDOSCext
Min 200 90
Typical 440 220
Max 12000 5000
Unit nF nF
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 247
Electrical Characteristics
A.3
Reset and Oscillator
This section summarizes the electrical characteristics of the various startup scenarios for the Oscillator.
A.3.1
Startup
Table A-11 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in Chapter 6, "Clocks and Reset Generator (CRG)".
Table A-11. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num 1 2 3 C T POR deassert level T POR assert level D Reset input pulse width, minimum input time Rating Symbol VPORD VPORA PWRSTL Min -- 0.97 2 Typ -- -- -- Max 2.07 -- -- Unit V V tosc
A.3.1.1
POR
The release level VPORD (see Table A-9) and the assert level VPORA (see Table A-9) are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator is started.
A.3.1.2
LVR
The assert level VLVRA (see Table A-9) is derived from the VDD Supply. After releasing the LVR reset, the oscillator is started..
A.3.1.3
External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CC starts operations, if there was an oscillation before reset.
MFR4300 Data Sheet, Rev. 3 248 Freescale Semiconductor
Electrical Characteristics
A.3.2
Oscillator
The device features an internal Pierce oscillator with a clock monitor. A clock monitor failure is asserted if the clock signal is below the Clock Monitor Assert Frequency, fCMFA.
Table A-12. Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 4 5 6 7 8 9 10 11
1
Rating
Symbol fOSC iOSC fCMAF fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS
Min 0.5 100 50 0.5 9.5 9.5 -- -- -- --
Typ -- -- 100 -- -- -- -- -- 7 TBD
Max 40 -- 200 50 -- -- 1 1 -- --
Unit MHz A kHz MHz ns ns ns ns pF V
C Crystal oscillator range (Pierce) 1 P Startup Current P Clock monitor assert frequency P External square wave input frequency D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Pierce mode on EXTAL Pin
Depending on the crystal a damping series resistor might be necessary
A.4
Asynchronous Memory Interface Timing
The CC AMI Interface read/write timing diagram is shown in the following figures. * Writing to the device is accomplished when Chip Enable (CE#) and Write Enable (WE#) inputs are LOW (asserted). * Reading from the device is accomplished when Chip Enable (CE#) and Output Enable (OE#) are LOW (asserted) while the Write Enable (WE#) is HIGH (deasserted). * The input/output pins D[15:0] are in a high-impedance state when the device is not selected (CE# is HIGH), the outputs are disabled (OE# HIGH) or during a write operation (CE# LOW, and WE# LOW).
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 249
Electrical Characteristics
tRC
tLOE
CE# `or' OE# tSAR A[12:1] tHAR
tHOE
ADDRESS tLZOE
tHZOE DATA
D[15:0] tWEOE WE#
tDOE
tOEWE
Figure A-2. AMI Interface Read Timing Diagram1 tWC
tLWE
CE# `or' WE# tSAW A[12:1]
tHWE
tHAW
ADDRESS
BSEL[1:0]
BYTE SELECT tSD tHD
D[15:0] tOEWE OE#
DATA tWEOE
Figure A-3. AMI Interface Write Timing Diagram2
1. "CE# `or' OE#" is a logical OR of the chip enable (CE#) and output enable (OE#) inputs. 2. "CE# `or' WE#" is a logical OR of the chip enable (CE#) and write enable (WE#) inputs.
MFR4300 Data Sheet, Rev. 3 250 Freescale Semiconductor
Electrical Characteristics
Table A-13. AMI Interface AC Switching Characteristics Over the Operating Range1
Characteristic Symbol Min Read Cycle Read Time Cycle Address Setup Read Address Hold Read OE# LOW to Data valid OE# LOW time OE# HIGH time OE# LOW to Low-Z OE# HIGH to High-Z WE# HIGH to OE# LOW tRC tSAR tHAR tDOE tLOE tHOE tLZOE tHZOE tWEOE 1 x tAMI_CLK Write Cycle Write Time Cycle Address Setup Write Address Hold Write Data Setup Data Hold WE# LOW time WE# HIGH time OE# HIGH to WE# LOW
1
Max
Unit
2.5 x tAMI_CLK + 32 5 5 2.5 x tAMI_CLK + 23 2.5 x tAMI_CLK + 272 5 5 15
ns ns ns ns ns ns ns ns ns
tWC tSAW tHAW tSD tHD tLWE tHWE tOEWE
3 x tAMI_CLK + 10 5 5 5 5 1.5 x tAMI_CLK + 5 0.5 x tAMI_CLK + 5 0
ns ns ns ns ns ns ns ns
tAMI_CLK is the period in ns of the CHI and host interface clock selected by IF_SEL[1:0] as described in Table 2-6. 2 Depends on duty cycle of the CHI and host interface clock: t LOE = (3.0 x tAMI_CLK) - tAMI_CLK_HIGH + 27, where tAMI_CLK_HIGH is the period in ns of the high phase of the CHI and host interface clock.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 251
Electrical Characteristics
A.5
HCS12 Interface Timing
tLEC ECLK tHDA PAD[15:0] tSA tHA tDEC tHEC
tSDR
DATA
tHDR
ADDRESS
XADDR[19:14]
ADDRESS
tDRW
R/W
tSRW
tHRW
ACS[2:0] Figure A-4. HCS12 Interface Read Timing Diagram tLEC ECLK tSA PAD[15:0] tHA tDDW DATA tHDW XADDR[19:14] ADDRESS tHEC
ADDRESS
tDRW
R/W
tSRW
tHRW
ACS[2:0] tDLS LSTRB
tSLS
LOW STROBE
tHLS
Figure A-5. HCS12 Interface Write Timing Diagram
MFR4300 Data Sheet, Rev. 3 252 Freescale Semiconductor
Electrical Characteristics
Table A-14. HCS12 Interface AC Switching Characteristics Over the Operating Range1
Characteristic Pulse width, ECLK Low Pulse width, ECLK High Address valid time to ECLK rise Write Data delay time Write Data hold time RW delay time RW valid time to ECLK rise RW hold time Data hold to address Multiplexed Address hold time ECLK high access time (ECLK high to Read Data valid) Read Data setup time Read Data hold time Low strobe delay time Low strobe valid to ECLK rise Low strobe hold time
1 2
Symbol tLEC tHEC tSA tDDW tHDW tDRW tSRW tHRW tHDA tHA tDEC tSDR tHDR tDLS tSLS tHLS
Min 30 992 11 -- 80 -- 14 2 2 2 50 13 0 -- 14 2
Max -- -- -- 70
Unit ns ns ns ns ns
7 -- -- -- -- 90 -- -- 7 -- --
ns ns ns ns ns ns ns ns ns ns ns
Based on fCLK_CC = 40 MHz. Depends on duty cycle of EXTAL/CLK_CC: tHEC = 99 + (tCLK_CC x 0.5) - tCLK_CC_HIGH, where tCLK_CC is the period in ns of EXTAL/CLK_CC and tCLK_CC_HIGH is the period in ns of the high phase of EXTAL/CLK_CC.
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 253
Electrical Characteristics
MFR4300 Data Sheet, Rev. 3 254 Freescale Semiconductor
Package Information
Appendix B Package Information
B.1 64-pin LQFP package
Figure B-1. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 1)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 255
Package Information
Figure B-2. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 2)
MFR4300 Data Sheet, Rev. 3 256 Freescale Semiconductor
Package Information
Figure B-3. 64-pin LQFP Mechanical Dimensions (Case N 840F-02) (Page 3)
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 257
Package Information
MFR4300 Data Sheet, Rev. 3 258 Freescale Semiconductor
Printed Circuit Board Layout Recommendations
Appendix C Printed Circuit Board Layout Recommendations
The PCB must be laid out carefully to ensure proper operation of the voltage regulator and the CC. The following rules must be observed: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (Cd). * The central point of the ground star should be the VSSR pin. * Low-ohmic low-inductance connections should be used between VSSX and VSSR. * VSSOSC must be directly connected to VSSR. * Traces of VSSOSC, EXTAL and XTAL must be kept as short as possible. Occupied board area for C1, C2, C3 and Q should be as small as possible. * Other signals or supply lines should not be routed under the area occupied by C1, C2, C3, and Q and the connection area of the CC. * The central power input should be fed in at the VDDA/VSSA pins. Figure C-1 shows a recommended PCB layout (64-pin LQFP) for standard Pierce oscillator mode, while Table C-1 provides suggested values for the external components.
Table C-1. Suggested External Component Values
Component C1 C2 C3 C4 Cd Cload RB RS Q Purpose OSC load cap OSC load cap VDDOSC filter cap VDDA filter cap VDDR, VDDX filter cap VDD2_5 filter cap OSC resistance OSC resistance Quartz NDK NX8045GA Type ceramic X7R ceramic X7R ceramic X7R ceramic X7R ceramic X7R/tantalum ceramic X7R Value 2pF 2pF 100- 220nF 100- 220nF 100- 220nF 100- 220nF 1 M 0 (i.e. short-circuit) 40 MHz
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 259
Printed Circuit Board Layout Recommendations
VDDA
VSSA
Cload
Cd
VDD2_5
Cd
VSS2_5
VDDX3 VSSX3
VSSX2 Cd Cd VDDX1 VSSX1 VDDX4 Cd VDDX2
Cd
C3
VSSR
Rs VSSX4 Rb
VDDR Q
Suggested component values: Q: NDK NX8045GA - 40MHz C1 = C2 = 2pF Rb = 1M Rs = 0 (i.e. short circuit) C3 = Cload = 220nF Cd = 100nF
VDDOSC C1 C2
VSSOSC
Figure C-1. Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode
MFR4300 Data Sheet, Rev. 3 260 Freescale Semiconductor
Appendix D Index of Registers
A Associated functions 60
F Features distinctive 59, 205, 221 Functions associated 60
I Initialization/application information 201, 203
M Maximum ratings (electrical) 240 message buffer individual 134
R Registers ASIC Version Number Register (AVNR) 208 Channel A Status Error Counter Register (CASERCR) 87 Channel B Status Error Counter Register (CBSERCR) 87 CHI Error Flag Register (CHIERFR) 84 Clock and Reset Status Register (CRSR) 223 Combined Interrupt Flag Register (CIFRR) 96 Cycle Counter Register (CYCTR) 94 Detection Enable Register (DER) 222 Global Interrupt Flag and Enable Register (GIFER) 77 Host Interface Pins Drive Strength Register (HIPDSR) 208 Host Interface Pins Pullup/down Control Register (HIPPCR) 211 Host Interface Pins Pullup/down Enable Register (HIPPER) 209 Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) 118 Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) 119 Macrotick Counter Register (MTCTR) 94 Message Buffer Configuration, Control, Status Registers (MBCCSRn) 128
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 261
Index of Registers
Message Buffer Cycle Counter Filter Registers (MBCCFRn) 130 Message Buffer Data Size Register (MBDSR) 74 Message Buffer Frame ID Registers (MBFIDRn) 131 Message Buffer Index Registers (MBIDXRn) 132 Message Buffer Interrupt Vector Register (MBIVEC) 86 Message Buffer Segment Size and Utilization Register (MBSSUTR) 74 Module Configuration Register (MCR) 68 Module Version Register (MVR) 68 MTS A Configuration Register (MTSACFR) 111 MTS B Configuration Register (MTSBCFR) 111 Network Management Vector Length Register (NMVLR) 102 Network Management Vector Registers (NMVR0-NMVR5) 101 Offset Correction Value Register (OFCORVR) 96 Part ID Register (PIDR) 208 Physical Layer Pins Drive Strength Register (PLPDSR) 209 Physical Layer Pins Pullup/down Control Register (PLPPCR) 213 Physical Layer Pins Pullup/down Enable Register (PLPPER) 212 Protocol Configuration Register 0 (PCR 0) 121 Protocol Configuration Register 1 (PCR 1) 121 Protocol Configuration Register 10 (PCR10) 123 Protocol Configuration Register 11 (PCR11) 124 Protocol Configuration Register 12 (PCR12) 124 Protocol Configuration Register 13 (PCR13) 124 Protocol Configuration Register 14 (PCR14) 124 Protocol Configuration Register 15 (PCR15) 125 Protocol Configuration Register 16 (PCR16) 125 Protocol Configuration Register 17 (PCR17) 125 Protocol Configuration Register 18 (PCR18) 125 Protocol Configuration Register 19 (PCR19) 125 Protocol Configuration Register 2 (PCR2) 122 Protocol Configuration Register 20 (PCR20) 126 Protocol Configuration Register 21 (PCR21) 126 Protocol Configuration Register 22 (PCR22) 126 Protocol Configuration Register 23 (PCR23) 126 Protocol Configuration Register 24 (PCR24) 126 Protocol Configuration Register 25 (PCR25) 127 Protocol Configuration Register 26 (PCR26) 127 Protocol Configuration Register 27 (PCR27) 127 Protocol Configuration Register 28 (PCR28) 127 Protocol Configuration Register 29 (PCR29) 128 Protocol Configuration Register 3 (PCR3) 122 Protocol Configuration Register 30 (PCR30) 128 Protocol Configuration Register 4 (PCR4) 122 Protocol Configuration Register 5 (PCR5) 122 Protocol Configuration Register 6 (PCR6) 122
MFR4300 Data Sheet, Rev. 3 262 Freescale Semiconductor
Index of Registers
Protocol Configuration Register 7 (PCR7) 123 Protocol Configuration Register 8 (PCR8) 123 Protocol Configuration Register 9 (PCR9) 123 Protocol Configuration Registers 119 Protocol Interrupt Enable Register 0 (PIER0) 82 Protocol Interrupt Enable Register 1 (PIER1) 83 Protocol Interrupt Flag Register 0 (PIFR0) 79 Protocol Interrupt Flag Register 1 (PIFR1) 81 Protocol Operation Control Register (POCR) 75 Protocol Status Register 0 (PSR0) 88 Protocol Status Register 1 (PSR1) 89 Protocol Status Register 2 (PSR2) 90 Protocol Status Register 3 (PSR3) 92 Rate Correction Value Register (RTCORVR) 95 Receive FIFO A Read Index Register (RFARIR) 114 Receive FIFO B Read Index Register (RFBRIR) 115 Receive FIFO Depth and Size Register (RFDSR) 114 Receive FIFO Frame ID Rejection Filter Mask Register 117 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) 116 Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) 116 Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) 115 Receive FIFO Range Filter Configuration Register (RFRFCFR) 117 Receive FIFO Range Filter Control Register (RFRFCTR) 118 Receive FIFO Selection Register (RFSR) 113 Receive FIFO Start Index Register (RFSIR) 113 Receive Shadow Buffer Index Register (RSBIR) 112 Slot Counter Channel A Register (SLTCTAR) 95 Slot Counter Channel B Register (SLTCTBR) 95 Slot Status Counter Condition Register (SSCCR) 107 Slot Status Counter Registers (SSCR0-SSCR3) 110 Slot Status Registers (SSR0-SSR7) 109 Slot Status Selection Register (SSSR) 106 Strobe Port Control Register (STBPCR) 73 Strobe Signal Control Register (STBSCR) 70 Sync Frame Counter Register (SFCNTR) 98 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR) 101 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) 101 Sync Frame Table Configuration, Control, Status Register (SFTCCSR) 99 Sync Frame Table Offset Register (SFTOR) 98 Timer 1 Cycle Set Register (TI1CYSR) 104 Timer 1 Macrotick Offset Register (TI1MTOR) 104 Timer 2 Configuration Register 0 (TI2CR0) 105 Timer 2 Configuration Register 1 (TI2CR1) 106 Timer Configuration and Control Register (TICCR) 103
MFR4300 Data Sheet, Rev. 3 Freescale Semiconductor 263
Index of Registers
MFR4300 Data Sheet, Rev. 3 264 Freescale Semiconductor
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Rev. 3 12/2006
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